Datasheet AD7810 (Analog Devices) - 9

AD7810 POWER-UP TIMES OPERATING MODES
The AD7810 has a 1.5 µs power-up time. When VDD is first
Mode 1 Operation (High Speed Sampling)
connected, the AD7810 is in a low current mode of operation. When the AD7810 is used in this mode of operation, the part is In order to carry out a conversion, the AD7810 must first be not powered down between conversions. This mode of opera- powered up. The ADC is powered up by a rising edge on the tion allows high throughput rates to be achieved. The timing CONVST pin. A conversion is initiated on the falling edge of diagram in Figure 14 shows how this optimum throughput rate CONVST. Figure 12 shows how to power up the AD7810 when is achieved by bringing the CONVST signal high before the end VDD is first connected or after the AD7810 is powered down of the conversion. The AD7810 leaves its tracking mode and using the CONVST pin. goes into hold on the falling edge of CONVST. A conversion is Care must be taken to ensure that the CONVST pin of the also initiated at this time. The conversion takes 2.3 µs to complete. AD7810 is logic low when V At this point, the result of the current conversion is latched into the DD is first applied. serial shift register, and the state of the CONVST signal checked. The CONVST signal should be high at the end of the conversion
MODE 1 (CONVST IDLES HIGH) V
to prevent the part from powering down.
DD tPOWER-UP < 1
␮
s 1.5
␮
s t CONVST 1 CONVST MODE 2 (CONVST IDLES LOW) A B t2 VDD tPOWER-UP SCLK 1.5
␮
s CONVST D
Figure 12. Power-Up Times
OUT CURRENT CONVERSION RESULT
Figure 14. Mode 1 Operation Timing
POWER VS. THROUGHPUT RATE
By operating the AD7810 in Mode 2, the average power con- The serial port on the AD7810 is enabled on the rising edge of sumption of the AD7810 decreases at lower throughput rates. the CONVST signal (see Serial Interface section). As explained Figure 13 shows how the automatic power-down is implemented earlier, this rising edge should occur before the end of the con- using the CONVST signal to achieve the optimum power per- version process if the part is not to be powered down. A serial formance for the AD7810. As the throughput rate is reduced, the read can take place at any stage after the rising edge of CONVST. device remains in its power-down state longer and the average If a serial read is initiated before the end of the current con- power consumption over time drops accordingly. version process (i.e., at time “A”), the result of the previous conversion is shifted out on the DOUT pin. It is possible to allow the serial read to extend beyond the end of a conversion. In this
tCONVERT t 2.3
␮
s
case the new data will not be latched into the output shift regis-
POWER-UP 1.5 POWER-DOWN
␮
s
ter until the read has finished. The dynamic performance of the
CONVST
AD7810 typically degrades by up to 3 dBs while reading during a conversion. If the user waits until the end of the conversion
tCYCLE
process, i.e., 2.3 µs after falling edge of CONVST (Point “B”),
100
␮
s @ 10kSPS
before initiating a read, the current conversion result is shifted out. Figure 13. Automatic Power-Down For example, if the AD7810 is operated in a continuous sampling mode with a throughput rate of 10 kSPS, the power consump- tion is calculated as follows. The power dissipation during normal operation is 9 mW, VDD = 3 V. If the power-up time is 1.5 µs and the conversion time is 2.3 µs, the AD7810 can be said to dissipate 9 mW for 3.8 µs (worst case) during each conversion cycle. If the throughput rate is 10 kSPS, the cycle time is 100 µs and the average power dissipated during each cycle is (3.8/100) × (9 mW) = 342 µW. Figure 2 shows a graph of Power vs. Throughput. –8– REV. B