Datasheet AD5379 (Analog Devices)

40-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage-Output DAC AD5379 FEATURES Interface options: 40-channel DAC in 13 mm × 13 mm 108-lead CSPBGA Parallel interface Guaranteed monotonic to 14 bits DSP/microcontroller-compatible, 3-wire serial interface Buffered voltage outputs 2.5 V to 5.5 V JEDEC-compliant digital levels Output voltage span of 3.5 V × V SDO daisy-chaining option REF(+) Maximum output voltage span of 17.5 V Power-on reset System calibration function allowing user-programmable Digital reset (RESET pin and soft reset function) offset and gain Pseudo differential outputs relative to REFGND APPLICATIONS Clear function to user-defined REFGND (CLR pin) Level setting in automatic test equipment (ATE) Simultaneous update of DAC outputs (LDAC pin) Variable optical attenuators (VOA) DAC increment/decrement mode Optical switches Channel grouping and addressing features Industrial control systems FUNCTIONAL BLOCK DIAGRAM VCC VDD VSS AGND DGND LDAC VBIAS VREF1(+) VREF1(–) REFGND A1 POWER-ON AD5379 VBIAS RESET CLR RESET FIFOEN DCEN/WR INPUT DAC VOUT0 14 14 14 14 SYNC/CS REG REG DAC 0–1 / / / / 0–1 0–1 VOUT1 REG0 REG1 m REG0–1 14 FIFO / c REG0–1 DB13 SCLK/DB12 DIN/DB11 INPUT DAC 14 14 14 14 / REG / / REG DAC 2 / DB0 2 2 VOUT2 m REG2 VOUT3 RFACE A7 14 c REG2 14 / VOUT4 INTE / VOUT5 A0 INPUT DAC VOUT6 SER/PAR MACHINE 14 14 14 14 REG REG / / / / DAC 7 DIN ATE 7 7 VOUT7 T SCLK S m REG7 SDO 14 c REG7 / REFGND B1 VOUT8 INPUT DAC REFGND B2 14 14 14 14 REG REG DAC 8–9 / / / / REFGND C1 8–9 8–9 VOUT9 REFGND C2 VOUT10 m REG8–9 14 REFGND D1 c REG8–9 /
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4 REFGND D2 VOUT39 BUSY VREF2(+) VREF2(–) REFGND A2
03165-001 Figure 1. AD5379—Protected by U.S. Patent No. 5,969,657.
Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2004–2009 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS TABLE OF CONTENTS GENERAL DESCRIPTION SPECIFICATIONS AC CHARACTERISTICS TIMING CHARACTERISTICS SERIAL INTERFACE PARALLEL INTERFACE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL CHANNEL GROUPS TRANSFER FUNCTION VBIAS FUNCTION REFERENCE SELECTION Reference Selection Example CALIBRATION Calibration Example CLEAR FUNCTION Hardware Clear Software Clear /BUSY AND /LDAC FUNCTIONS FIFO VS. NON-FIFO OPERATION /BUSY INPUT FUNCTION POWER-ON RESET FUNCTION /RESET INPUT FUNCTION INCREMENT/DECREMENT FUNCTION INTERFACES PARALLEL INTERFACE / CS Pin /WR Pin REG1, REG0 Pins DB13 to DB0 Pins A7 to A0 Pins SERIAL INTERFACE /SYNC , DIN, SCLK DCEN SDO Standalone Mode Daisy-Chain Mode DATA DECODING ADDRESS DECODING POWER SUPPLY DECOUPLING POWER-ON TYPICAL APPLICATION CIRCUIT OUTLINE DIMENSIONS ORDERING GUIDE