Datasheet AD8139 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | Low Noise, Rail-to-Rail, Differential ADC Driver |
| 页数 / 页 | 27 / 9 — AD8139. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. –IN 1. … |
| 修订版 | C |
| 文件格式/大小 | PDF / 597 Kb |
| 文件语言 | 英语 |
AD8139. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. –IN 1. 8 +IN. VOCM 2. 7 NIC. TOP VIEW. V+ 3. 6 V–
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AD8139 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS –IN 1 8 +IN –IN 1 AD8139 8 +IN VOCM 2 7 NIC AD8139 VOCM 2 7 NIC TOP VIEW V+ 3 TOP VIEW 6 V– V+ 3 (Not to Scale) 6 V– (Not to Scale) +OUT 4 5 –OUT 4 5 –OUT +OUT NOTES NOTES 1. NIC = NO INTERNAL CONNECTION. 1. NIC = NO INTERNAL CONNECTION. 2. SOLDER THE EXPOSED PADDLE 2. SOLDER THE EXPOSED PADDLE
3
ON THE BACK OF THE PACKAGE ON THE BACK OF THE PACKAGE
03 -00
TO THE GROUND PLANE OR TO
1
TO THE GROUND PLANE OR TO
679 79-
A POWER PLANE.
04
A POWER PLANE.
046 Figure 5. 8-Lead SOIC Pin Configuration Figure 6. 8-Lead LFCSP Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 −IN Inverting Input. 2 VOCM An internal feedback loop drives the output common-mode voltage to be equal to the voltage applied to the VOCM pin, provided the operation of the amplifier remains linear. 3 V+ Positive Power Supply Voltage. 4 +OUT Positive Side of the Differential Output. 5 −OUT Negative Side of the Differential Output. 6 V− Negative Power Supply Voltage. 7 NIC No Internal Connection. 8 +IN Noninverting Input. 0 EP Exposed Paddle. Solder the exposed paddle on the back of the package to the ground plane or to a power plane. Rev. C | Page 8 of 26 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS VS = ±5 V, VOCM = 0 V VS = 5 V, VOCM = 2.5 V ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Maximum Power Dissipation ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION TYPICAL CONNECTION AND DEFINITION OF TERMS Output Balance APPLICATIONS INFORMATION ESTIMATING NOISE, GAIN, AND BANDWIDTH WITH MATCHED FEEDBACK NETWORKS Estimating Output Noise Voltage Voltage Gain Feedback Factor Notation Input Common-Mode Voltage Calculating Input Impedance Input Common-Mode Swing Considerations Bandwidth vs. Closed-Loop Gain Estimating DC Errors Other Impact of Mismatches in the Feedback Networks Driving a Capacitive Load Layout Considerations Terminating a Single-Ended Input Exposed Paddle (EP) OUTLINE DIMENSIONS ORDERING GUIDE
3
ON THE BACK OF THE PACKAGE ON THE BACK OF THE PACKAGE
03 -00
TO THE GROUND PLANE OR TO
1
TO THE GROUND PLANE OR TO
679 79-
A POWER PLANE.
04
A POWER PLANE.
046 Figure 5. 8-Lead SOIC Pin Configuration Figure 6. 8-Lead LFCSP Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 −IN Inverting Input. 2 VOCM An internal feedback loop drives the output common-mode voltage to be equal to the voltage applied to the VOCM pin, provided the operation of the amplifier remains linear. 3 V+ Positive Power Supply Voltage. 4 +OUT Positive Side of the Differential Output. 5 −OUT Negative Side of the Differential Output. 6 V− Negative Power Supply Voltage. 7 NIC No Internal Connection. 8 +IN Noninverting Input. 0 EP Exposed Paddle. Solder the exposed paddle on the back of the package to the ground plane or to a power plane. Rev. C | Page 8 of 26 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS VS = ±5 V, VOCM = 0 V VS = 5 V, VOCM = 2.5 V ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Maximum Power Dissipation ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION TYPICAL CONNECTION AND DEFINITION OF TERMS Output Balance APPLICATIONS INFORMATION ESTIMATING NOISE, GAIN, AND BANDWIDTH WITH MATCHED FEEDBACK NETWORKS Estimating Output Noise Voltage Voltage Gain Feedback Factor Notation Input Common-Mode Voltage Calculating Input Impedance Input Common-Mode Swing Considerations Bandwidth vs. Closed-Loop Gain Estimating DC Errors Other Impact of Mismatches in the Feedback Networks Driving a Capacitive Load Layout Considerations Terminating a Single-Ended Input Exposed Paddle (EP) OUTLINE DIMENSIONS ORDERING GUIDE