Datasheet MCP6051, MCP6052, MCP6054 (Microchip) - 3
| 制造商 | Microchip |
| 描述 | The Microchip Technology MCP6051/2/4 family of operational amplifiers (op amps) has low input offset voltage (±150 µV, maximum) and rail-to-rail input and output operation |
| 页数 / 页 | 40 / 3 — MCP6051/2/4. 1.0. ELECTRICAL CHARACTERISTICS. 1.1. Absolute Maximum … |
| 文件格式/大小 | PDF / 1.3 Mb |
| 文件语言 | 英语 |
MCP6051/2/4. 1.0. ELECTRICAL CHARACTERISTICS. 1.1. Absolute Maximum Ratings †. † Notice:. 4.1.2 “Input Voltage Limits”. 1.2
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MCP6051/2/4 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings †
VDD – VSS ..7.0V
† Notice:
Stresses above those listed under “Absolute Current at Input Pins ...±2 mA Maximum Ratings” may cause permanent damage to Analog Inputs (V the device. This is a stress rating only and functional IN+, VIN-)†† .. VSS – 1.0V to VDD + 1.0V operation of the device at those or any other conditions All Other Inputs and Outputs ... VSS – 0.3V to VDD + 0.3V above those indicated in the operational listings of this Difference Input Voltage .. |VDD – VSS| specification is not implied. Exposure to maximum Output Short-Circuit Current ...continuous rating conditions for extended periods may affect Current at Output and Supply Pins ..±30 mA device reliability. Storage Temperature ..-65°C to +150°C
††
See
4.1.2 “Input Voltage Limits”
Maximum Junction Temperature (TJ).. +150°C ESD protection on all pins (HBM; MM) .. ≥ 4 kV; 400V
1.2 Specifications TABLE 1-1: DC ELECTRICAL SPECIFICATIONS Electrical Characteristics
: Unless otherwise indicated, VDD = +1.8V to +6.0V, VSS= GND, TA= +25°C, VCM = VDD/2, V ≈ OUT VDD/2, VL = VDD/2 and RL = 100 kΩ to VL. (Refer to Figure 1-1).
Parameters Sym Min Typ Max Units Conditions Input Offset
Input Offset Voltage VOS -150 — +150 µV VDD = 3.0V, VCM = VDD/3 Input Offset Drift with Temperature ΔVOS/ΔTA — ±1.5 — µV/°C TA= -40°C to +85°C, VDD = 3.0V, VCM = VDD/3 ΔVOS/ΔTA — ±4.0 — µV/°C TA= +85°C to +125°C, VDD = 3.0V, VCM = VDD/3 Power Supply Rejection Ratio PSRR 70 87 — dB VCM = VSS
Input Bias Current and Impedance
Input Bias Current IB — ±1.0 100 pA IB — 60 — pA TA = +85°C IB — 1100 5000 pA TA = +125°C Input Offset Current IOS — ±1.0 — pA Common Mode Input Impedance ZCM — 1013||6 — Ω||pF Differential Input Impedance ZDIFF — 1013||6 — Ω||pF
Common Mode
Common Mode Input Voltage Range V − CMR VSS 0.2 — VDD+0.2 V VDD = 1.8V
(Note 1 )
V − CMR VSS 0.3 — VDD+0.3 V VDD = 6.0V
(Note 1 )
Common Mode Rejection Ratio CMRR 74 90 — dB VCM = -0.2V to 2.0V, VDD = 1.8V 74 91 — dB VCM = -0.3V to 6.3V, VDD = 6.0V 72 87 — dB VCM = 3.0V to 6.3V, VDD = 6.0V 74 89 — dB VCM = -0.3V to 3.0V, VDD = 6.0V
Note 1:
Figure 2-13 shows how VCMR changed across temperature. © 2010 Microchip Technology Inc. DS22182B-page 3 Document Outline MCP6051/2/4 Applications Design Aids Typical Application Description Package Types 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Specifications TABLE 1-1: DC electrical specifications TABLE 1-2: AC Electrical Specifications TABLE 1-3: temperature specifications 1.3 Test Circuits EQUATION 1-1: FIGURE 1-1: AC and DC Test Circuit for Most Specifications. Notes: 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage with VDD = 3.0V. FIGURE 2-2: Input Offset Voltage Drift with VDD = 3.0V and TA £ +85°C. FIGURE 2-3: Input Offset Voltage Drift with VDD = 3.0V and TA ³ +85°C. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 6.0V. FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 3.0V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.8V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: Input Offset Voltage vs. Power Supply Voltage. FIGURE 2-9: Input Noise Voltage Density vs. Frequency. FIGURE 2-10: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-11: CMRR, PSRR vs. Frequency. FIGURE 2-12: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-13: Common Mode Input Voltage Range Limit vs. Ambient Temperature. FIGURE 2-14: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-15: Input Bias Current vs. Common Mode Input Voltage. FIGURE 2-16: Quiescent Current vs Ambient Temperature with VCM = 0.9VDD. FIGURE 2-17: Quiescent Current vs. Power Supply Voltage with VCM = 0.9VDD. FIGURE 2-18: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-19: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-20: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-21: Channel-to-Channel Separation vs. Frequency (MCP6052/4 only). FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-24: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-25: Ouput Short Circuit Current vs. Power Supply Voltage. FIGURE 2-26: Output Voltage Swing vs. Frequency. FIGURE 2-27: Ratio of Output Voltage Headroom to Output Current vs. Output Current. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Slew Rate vs. Ambient Temperature. FIGURE 2-30: Small Signal Non-Inverting Pulse Response. FIGURE 2-31: Small Signal Inverting Pulse Response. FIGURE 2-32: Large Signal Non-Inverting Pulse Response. FIGURE 2-33: Large Signal Inverting Pulse Response. FIGURE 2-34: The MCP6051/2/4 Shows No Phase Reversal. FIGURE 2-35: Closed Loop Output Impedance vs. Frequency. FIGURE 2-36: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) Notes: 4.0 Application Information 4.1 Rail-to-Rail Input 4.1.1 Phase Reversal 4.1.2 Input Voltage Limits FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.1.3 Input Current Limits FIGURE 4-3: Protecting the Analog Inputs. 4.1.4 Normal Operation 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 1. Non-inverting Gain and Unity-Gain Buffer: a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b) Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the common mode input voltage. 2. Inverting Gain and Transimpedance Gain Amplifiers (convert current to voltage, such as photo detectors): a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface. 4.7 Application Circuits 4.7.1 Gyrator FIGURE 4-8: Gyrator. 4.7.2 Instrumentation Amplifier FIGURE 4-9: Two Op Amp Instrumentation Amplifier. 4.7.3 Precision Comparator FIGURE 4-10: Precision, Non-inverting Comparator. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Microchip Advanced Part Selector (MAPS) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes Notes: 6.0 Packaging Information Features 6.1 Package Marking Information 30 µA, High Precision Op Amps Appendix A: Revision History Revision B (December 2010) 1. Added new SOT-23-5 package type for MCP6051 device. 2. Corrected Figures 2-13, 2-22, 2-23, 2-24 and 2-28 in Section 2.0 “Typical Performance Curves”. 3. Modified Table 3-1 to show the pin column for MCP6051, SOT-23-5 package. 4. Updated Section 4.1.2 “Input Voltage Limits”. 5. Added Section 4.1.3 “Input Current Limits”. 6. Added new document item in Section 5.5 “Application Notes”. 7. Updated the package markings information and drawings. 8. Updated the Product Identification System page. Revision A (May 2009) Notes: a) MCP6051T-E/OT: Tape and Reel, 5LD SOT-23 package b) MCP6051-E/SN: 8LD SOIC package c) MCP6051T-E/SN: Tape and Reel, 8LD SOIC package d) MCP6051T-E/MNY: Tape and Reel, 8LD 2x3 TDFN package a) MCP6052-E/SN: 8LD SOIC package b) MCP6052T-E/SN: Tape and Reel, 8LD SOIC package c) MCP6052T-E/MNY: Tape and Reel 8LD 2x3 TDFN package a) MCP6054-E/SL: 14LD SOIC package b) MCP6054T-E/SL: Tape and Reel, 14LD SOIC package c) MCP6054-E/ST: 14LD TSSOP package d) MCP6054T-E/ST: Tape and Reel, 14LD TSSOP package Notes: Worldwide Sales and Service Trademarks Worldwide Sales
MCP6051/2/4 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings †
VDD – VSS ..7.0V
† Notice:
Stresses above those listed under “Absolute Current at Input Pins ...±2 mA Maximum Ratings” may cause permanent damage to Analog Inputs (V the device. This is a stress rating only and functional IN+, VIN-)†† .. VSS – 1.0V to VDD + 1.0V operation of the device at those or any other conditions All Other Inputs and Outputs ... VSS – 0.3V to VDD + 0.3V above those indicated in the operational listings of this Difference Input Voltage .. |VDD – VSS| specification is not implied. Exposure to maximum Output Short-Circuit Current ...continuous rating conditions for extended periods may affect Current at Output and Supply Pins ..±30 mA device reliability. Storage Temperature ..-65°C to +150°C
††
See
4.1.2 “Input Voltage Limits”
Maximum Junction Temperature (TJ).. +150°C ESD protection on all pins (HBM; MM) .. ≥ 4 kV; 400V
1.2 Specifications TABLE 1-1: DC ELECTRICAL SPECIFICATIONS Electrical Characteristics
: Unless otherwise indicated, VDD = +1.8V to +6.0V, VSS= GND, TA= +25°C, VCM = VDD/2, V ≈ OUT VDD/2, VL = VDD/2 and RL = 100 kΩ to VL. (Refer to Figure 1-1).
Parameters Sym Min Typ Max Units Conditions Input Offset
Input Offset Voltage VOS -150 — +150 µV VDD = 3.0V, VCM = VDD/3 Input Offset Drift with Temperature ΔVOS/ΔTA — ±1.5 — µV/°C TA= -40°C to +85°C, VDD = 3.0V, VCM = VDD/3 ΔVOS/ΔTA — ±4.0 — µV/°C TA= +85°C to +125°C, VDD = 3.0V, VCM = VDD/3 Power Supply Rejection Ratio PSRR 70 87 — dB VCM = VSS
Input Bias Current and Impedance
Input Bias Current IB — ±1.0 100 pA IB — 60 — pA TA = +85°C IB — 1100 5000 pA TA = +125°C Input Offset Current IOS — ±1.0 — pA Common Mode Input Impedance ZCM — 1013||6 — Ω||pF Differential Input Impedance ZDIFF — 1013||6 — Ω||pF
Common Mode
Common Mode Input Voltage Range V − CMR VSS 0.2 — VDD+0.2 V VDD = 1.8V
(Note 1 )
V − CMR VSS 0.3 — VDD+0.3 V VDD = 6.0V
(Note 1 )
Common Mode Rejection Ratio CMRR 74 90 — dB VCM = -0.2V to 2.0V, VDD = 1.8V 74 91 — dB VCM = -0.3V to 6.3V, VDD = 6.0V 72 87 — dB VCM = 3.0V to 6.3V, VDD = 6.0V 74 89 — dB VCM = -0.3V to 3.0V, VDD = 6.0V
Note 1:
Figure 2-13 shows how VCMR changed across temperature. © 2010 Microchip Technology Inc. DS22182B-page 3 Document Outline MCP6051/2/4 Applications Design Aids Typical Application Description Package Types 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Specifications TABLE 1-1: DC electrical specifications TABLE 1-2: AC Electrical Specifications TABLE 1-3: temperature specifications 1.3 Test Circuits EQUATION 1-1: FIGURE 1-1: AC and DC Test Circuit for Most Specifications. Notes: 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage with VDD = 3.0V. FIGURE 2-2: Input Offset Voltage Drift with VDD = 3.0V and TA £ +85°C. FIGURE 2-3: Input Offset Voltage Drift with VDD = 3.0V and TA ³ +85°C. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 6.0V. FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 3.0V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.8V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: Input Offset Voltage vs. Power Supply Voltage. FIGURE 2-9: Input Noise Voltage Density vs. Frequency. FIGURE 2-10: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-11: CMRR, PSRR vs. Frequency. FIGURE 2-12: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-13: Common Mode Input Voltage Range Limit vs. Ambient Temperature. FIGURE 2-14: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-15: Input Bias Current vs. Common Mode Input Voltage. FIGURE 2-16: Quiescent Current vs Ambient Temperature with VCM = 0.9VDD. FIGURE 2-17: Quiescent Current vs. Power Supply Voltage with VCM = 0.9VDD. FIGURE 2-18: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-19: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-20: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-21: Channel-to-Channel Separation vs. Frequency (MCP6052/4 only). FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-24: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-25: Ouput Short Circuit Current vs. Power Supply Voltage. FIGURE 2-26: Output Voltage Swing vs. Frequency. FIGURE 2-27: Ratio of Output Voltage Headroom to Output Current vs. Output Current. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Slew Rate vs. Ambient Temperature. FIGURE 2-30: Small Signal Non-Inverting Pulse Response. FIGURE 2-31: Small Signal Inverting Pulse Response. FIGURE 2-32: Large Signal Non-Inverting Pulse Response. FIGURE 2-33: Large Signal Inverting Pulse Response. FIGURE 2-34: The MCP6051/2/4 Shows No Phase Reversal. FIGURE 2-35: Closed Loop Output Impedance vs. Frequency. FIGURE 2-36: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) Notes: 4.0 Application Information 4.1 Rail-to-Rail Input 4.1.1 Phase Reversal 4.1.2 Input Voltage Limits FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.1.3 Input Current Limits FIGURE 4-3: Protecting the Analog Inputs. 4.1.4 Normal Operation 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 1. Non-inverting Gain and Unity-Gain Buffer: a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b) Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the common mode input voltage. 2. Inverting Gain and Transimpedance Gain Amplifiers (convert current to voltage, such as photo detectors): a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface. 4.7 Application Circuits 4.7.1 Gyrator FIGURE 4-8: Gyrator. 4.7.2 Instrumentation Amplifier FIGURE 4-9: Two Op Amp Instrumentation Amplifier. 4.7.3 Precision Comparator FIGURE 4-10: Precision, Non-inverting Comparator. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Microchip Advanced Part Selector (MAPS) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes Notes: 6.0 Packaging Information Features 6.1 Package Marking Information 30 µA, High Precision Op Amps Appendix A: Revision History Revision B (December 2010) 1. Added new SOT-23-5 package type for MCP6051 device. 2. Corrected Figures 2-13, 2-22, 2-23, 2-24 and 2-28 in Section 2.0 “Typical Performance Curves”. 3. Modified Table 3-1 to show the pin column for MCP6051, SOT-23-5 package. 4. Updated Section 4.1.2 “Input Voltage Limits”. 5. Added Section 4.1.3 “Input Current Limits”. 6. Added new document item in Section 5.5 “Application Notes”. 7. Updated the package markings information and drawings. 8. Updated the Product Identification System page. Revision A (May 2009) Notes: a) MCP6051T-E/OT: Tape and Reel, 5LD SOT-23 package b) MCP6051-E/SN: 8LD SOIC package c) MCP6051T-E/SN: Tape and Reel, 8LD SOIC package d) MCP6051T-E/MNY: Tape and Reel, 8LD 2x3 TDFN package a) MCP6052-E/SN: 8LD SOIC package b) MCP6052T-E/SN: Tape and Reel, 8LD SOIC package c) MCP6052T-E/MNY: Tape and Reel 8LD 2x3 TDFN package a) MCP6054-E/SL: 14LD SOIC package b) MCP6054T-E/SL: Tape and Reel, 14LD SOIC package c) MCP6054-E/ST: 14LD TSSOP package d) MCP6054T-E/ST: Tape and Reel, 14LD TSSOP package Notes: Worldwide Sales and Service Trademarks Worldwide Sales