Datasheet Summary SAM D21EL, SAM D21GL (Microchip) - 9

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32-bit ARM-Based Microcontrollers 4. Block Diagram
IOBUS 256/128/64/32KB 32/16/8/4KB
CORTEX-M0+
NVM RAM SWCLK SERIAL
PROCESSOR
BUFFER NVM SWDIO WIRE
Fmax 48 MHz
MICRO SRAM CONTROLLER CONTROLLER TRACE Cache DEVICE SERVICE UNIT M M S S M HIGH SPEED DMA BUS MATRIX PERIPHERAL ACCESS CONTROLLER S S S AHB-APB AHB-APB AHB-APB BRIDGE B BRIDGE A BRIDGE C PERIPHERAL PERIPHERAL ACCESS CONTROLLER ACCESS CONTROLLER SYSTEM CONTROLLER DMA PAD0 T PAD1 VREF 6 x SERCOM 6 x SERCOM PAD2 POR PAD3 BOD33 OSCULP32K OSC32K DMA OSC8M WO0 5 8 x Timer Counter x TIMER / COUNTER WO1 DFLL48M XIN XOUT XOSC FDPLL96M T DMA WO0 3 x TIMER / COUNTER WO1 POR FOR CONTROL POWER MANAGER (2) WOn CLOCK DMA AIN[19..0] CONTROLLER 18-CHANNEL VREFA 12-bit ADC 350KSPS RESET SLEEP EVENT SYSTEM VREFB RESETN CONTROLLER CONTROLLER CMP[1..0] GENERIC CLOCK 4 x ANALOG AIN[3..0] GCLK_IO[7..0] CONTROLLER COMPARATORS REAL TIME COUNTER DMA VOUT WATCHDOG 10-bit DAC TIMER VREFA EXTINT[15..0] EXTERNAL INTERRUPT NMI CONTROLLER 1. Some products have different number of SERCOM instances, Timer/Counter instances and ADC signals. Refer to the Configuration Summary. 2. The three TCC instances have different configurations, including the number of Waveform Output (WO) lines. Refer to the TCC Configutations for details.
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Configuration Summary © 2017 Microchip Technology Inc.
Datasheet Summary
40001885A-page 9 Document Outline Introduction Features Table of Contents 1. Description 2. Configuration Summary 3. Ordering Information 3.1. SAM D21ExL 3.2. SAM D21GxL 3.3. Device Identification 4. Block Diagram 5. Pinout 5.1. SAM D21GxL 5.1.1. QFN48 5.2. SAM D21ExL 5.2.1. QFN32 / TQFP32 6. Product Mapping 7. Processor And Architecture 7.1. Cortex M0+ Processor 7.1.1. Cortex M0+ Configuration 7.1.2. Cortex-M0+ Peripherals 7.1.3. Cortex-M0+ Address Map 7.1.4. I/O Interface 7.1.4.1. Overview 7.1.4.2. Description 7.2. Nested Vector Interrupt Controller 7.2.1. Overview 7.2.2. Interrupt Line Mapping 7.3. Micro Trace Buffer 7.3.1. Features 7.3.2. Overview 7.4. High-Speed Bus System 7.4.1. Features 7.4.2. Configuration 7.4.3. SRAM Quality of Service 7.5. AHB-APB Bridge 7.6. PAC - Peripheral Access Controller 7.6.1. Overview 7.6.2. Register Description 7.6.2.1. PAC0 Register Description 7.6.2.1.1. Write Protect Clear 7.6.2.1.2. Write Protect Set 7.6.2.2. PAC1 Register Description 7.6.2.2.1. Write Protect Clear 7.6.2.2.2. Write Protect Set 7.6.2.3. PAC2 Register Description 7.6.2.3.1. Write Protect Clear 7.6.2.3.2. Write Protect Set 8. Packaging Information 8.1. Thermal Considerations 8.1.1. Thermal Resistance Data 8.1.2. Junction Temperature 8.2. Package Drawings 8.2.1. 48 pin QFN 8.2.2. 32 pin TQFP 8.2.3. 32 pin QFN 8.3. Soldering Profile The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Certified by DNV Worldwide Sales and Service