Datasheet MCP3202 (Microchip) - 8

MCP3202 Note:
Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE, TA = +25°C. 1.0 1.0 0.8 0.8 VDD = 2.7V 0.6 0.6 fSAMPLE = 50 ksps
)
0.4
)
0.4
B B
0.2
S S
0.2
L L (
0.0
(
0.0 -0.2 -0.2
DNL DNL
-0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096
Digital Code Digital Code FIGURE 2-13:
Differential Nonlinearity
FIGURE 2-16:
Differential Nonlinearity (DNL) vs. Code (Representative Part). (DNL) vs. Code (Representative Part, VDD = 2.7V). 1.0 1.0 0.8 V 0.8 DD = 2.7V 0.6 f 0.6 SAMPLE = 50 ksps
)
0.4 Positive DNL Positive DNL
B )
0.4
S
0.2
B L S
0.2 0.0
L
0.0 -0.2
DNL (
-0.2 Negative DNL -0.4
DNL (
-0.4 Negative DNL -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temperature (°C) Temperature (°C) FIGURE 2-14:
Differential Nonlinearity
FIGURE 2-17:
Differential Nonlinearity (DNL) vs. Temperature. (DNL) vs. Temperature (VDD = 2.7V). 2.0 2.0 1.5 1.8
)
f 1.0
B
SAMPLE = 10 ksps
)
1.6 fSAMPLE = 100 ksps
S B S
fSAMPLE = 50 ksps 0.5
(L
1.4
L r (
1.2 0.0
rror
1.0
rro
-0.5
in E
0.8 -1.0
Ga
0.6
fset E
-1.5 f
Of
0.4 SAMPLE = 100 ksps fSAMPLE = 10 ksps f 0.2 -2.0 SAMPLE = 50 ksps 0.0 2.5 3.0 3.5 4.0 4.5 5.0 2.5 3.0 3.5 4.0 4.5 5.0
VDD(V) VDD(V) FIGURE 2-15:
Gain Error vs. VDD.
FIGURE 2-18:
Offset Error vs. VDD. DS21034F-page 8  1999-2011 Microchip Technology Inc. Document Outline MCP3202 - 2.7V Dual Channel 12-Bit A/D Converter with SPI Serial Interface Functional Block Diagram Package Types 1.0 Electrical Characteristics Absolute Maximum Ratings † FIGURE 1-1: Serial Timing. FIGURE 1-2: Test Circuits. 2.0 Typical Performance Characteristics FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample Rate. FIGURE 2-2: Integral Nonlinearity (INL) vs. VDD. FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part). FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V). FIGURE 2-5: Integral Nonlinearity (INL) vs. VDD. FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V). FIGURE 2-7: Integral Nonlinearity (INL) vs. Temperature. FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate. FIGURE 2-9: Differential Nonlinearity (DNL) vs. VDD. FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature (VDD = 2.7V). FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (VDD = 2.7V). FIGURE 2-12: Differential Nonlinearity (DNL) vs. VDD. FIGURE 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part). FIGURE 2-14: Differential Nonlinearity (DNL) vs. Temperature. FIGURE 2-15: Gain Error vs. VDD. FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, VDD = 2.7V). FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature (VDD = 2.7V). FIGURE 2-18: Offset Error vs. VDD. FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-20: Signal-to-Noise Ratio (SNR) vs. Input Frequency. FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency. FIGURE 2-22: Offset Error vs. Temperature. FIGURE 2-23: Signal-to-Noise and Distortion (SINAD) vs. Input Frequency. FIGURE 2-24: Signal-to-Noise and Distortion (SINAD) vs. Signal Level. FIGURE 2-25: Effective Number of Bits (ENOB) vs. VDD. FIGURE 2-26: Spurious Free Dynamic Range (SFDR) vs. Input Frequency. FIGURE 2-27: Frequency Spectrum of 10 kHz input (Representative Part). FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency. FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency. FIGURE 2-30: Frequency Spectrum of 1 kHz input (Representative Part, VDD = 2.7V). FIGURE 2-31: IDD vs. VDD. FIGURE 2-32: IDD vs. Clock Frequency. FIGURE 2-33: IDD vs. Temperature. FIGURE 2-34: IDDS vs. VDD. FIGURE 2-35: IDDS vs. Temperature. FIGURE 2-36: Analog Input leakage current vs. Temperature. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Inputs (CH0/CH1) 3.2 Chip Select/Shutdown (CS/SHDN) 3.3 Serial Clock (CLK) 3.4 Serial Data Input (DIN) 3.5 Serial Data Output (DOUT) 4.0 Device Operation 4.1 Analog Inputs 4.2 Digital Output Code EQUATION 4-1: FIGURE 4-1: Analog Input Model. FIGURE 4-2: Maximum Clock Frequency vs. Input Resistance (RS) to maintain less than a 0.1 LSB deviation in INL from nominal conditions. 5.0 Serial Communications 5.1 Overview TABLE 5-1: Configuration Bits for the MCP3202 FIGURE 5-1: Communication with the MCP3202 using MSB first format only. FIGURE 5-2: Communication with MCP3202 using LSB first format. 6.0 Applications Information 6.1 Using the MCP3202 with Microcontroller (MCU) SPI Ports FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low). FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high). 6.2 Maintaining Minimum Clock Speed 6.3 Buffering/Filtering the Analog Inputs FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a 2nd order anti- aliasing filter for the signal being converted by the MCP3202. 6.4 Layout Considerations FIGURE 6-4: VDD traces arranged in a ‘Star’ configuration in order to reduce errors caused by current return paths. 7.0 Packaging Information 7.1 Package Marking Information Appendix A: Revision History Worldwide Sales and Service