Datasheet AD7740 (Analog Devices) - 8

AD7740 GENERAL DESCRIPTION VFC Modulator
The AD7740 is a CMOS synchronous Voltage-to-Frequency The analog input signal to the AD7740 is continuously sampled Converter (VFC) which uses a charge-balance conversion by a switched capacitor modulator whose sampling rate is set technique. The input voltage signal is applied to a proprietary by a master clock. The input signal may be buffered on-chip front-end based around an analog modulator which converts the (BUF = 1) before being applied to the sampling capacitor of the input voltage into an output pulse train. modulator. This isolates the sampling capacitor charging currents The part also contains an on-chip 2.5 V bandgap reference and from the analog input pin. operates from a single 3.3 V or 5 V supply. A block diagram of This system is a negative feedback loop that acts to keep the net the AD7740 is shown in Figure 3. charge on the integrator capacitor at zero, by balancing charge injected by the input voltage with charge injected by VREF. The
INTEGRATOR COMPARATOR
output of the comparator provides the digital input for the 1-bit
SWITCHED VIN CAPS
DAC, so that the system functions as a negative feedback loop
FOUT
that acts to minimize the difference signal. See Figure 5.
SWITCHED CAPS CLK AD7740 INTEGRATOR BUF GND COMPARATOR
Figure 3. Block Diagram
INPUT 1-BIT Input Amplifier Buffering and Voltage Range BITSTREAM
The analog input VIN can be buffered by setting BUF = 1. This presents a high impedance, typically 100 MΩ, which allows significant external source impedances to be tolerated. The VIN
AD7740 +VREF
voltage range is now 0.1 V to VDD – 0.2 V. By setting BUF = 0 the AD7740 input circuit accepts an analog input below GND
–VREF
and the analog input VIN has a voltage range from –0.15 V to Figure 5. Modulator Loop VDD + 0.15 V. In this case the input impedance is typically 650 kΩ. The digital data that represents the analog input voltage is con- tained in the duty cycle of the pulse train appearing at the output The transfer function for the AD7740 is represented by: of the comparator. The output is a pulse train whose frequency FOUT = 0.1 fCLKIN + 0.8 (VIN/VREF) fCLKIN depends on the analog input signal. A full-scale input gives an It is shown in Figure 4 for unbuffered mode. output frequency of 0.9 fCLKIN and zero-scale input gives an output frequency of 0.1 fCLKIN. The output allows simple inter-
OUTPUT
facing to either standard logic families or opto-couplers. The
FREQUENCY
pulsewidth of FOUT is fixed and is determined by the high period
FOUT FOUT MAX
of CLKIN. The pulse is synchronized to the rising edge of the
0.90 fCLKIN
clock signal. The delay time between the edge of CLKIN and the
AD7740
edge of FOUT is typically 35 ns. Figure 6 shows the waveform of this frequency output. (See TPC 8.)
fCLKIN FOUT = fCLKIN/2 VIN = VREF/2 0.10 fCLKIN FOUT = f FOUT MIN CLKIN/5 INPUT VIN = VREF/8 VOLTAGE –0.15V 0 VREF V VIN REF + 0.15V FOUT = f
Figure 4. Transfer Function
CLKIN 3/10 VIN = VREF/4 Sample Calculation: 3t 4t
V
CLKIN CLKIN
REF = 2.5 V, BUF = 0
AVERAGE FOUT IS fCLKIN 3/10 BUT THE ACTUAL PULSE STREAM VARIES
FOUT (min) = 0.1 fCLKIN + 0.8(–0.15/2.5) fCLKIN
BETWEEN fCLKIN/3 and fCLKIN/4
= 0.052 fCLKIN Figure 6. Frequency Output Waveforms FOUT (max) = 0.1 fCLKIN + 0.8(2.65/2.5) fCLKIN = 0.948 f If there is a step change in input voltage, there is a settling time CLKIN that must elapse before valid data is obtained. This is typically two CLKIN cycles. REV. C – 7 –