Datasheet AD650 (Analog Devices) - 9

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AD650 Data Sheet
The positive input voltage develops a current (IIN = VIN/RIN) that 3 − .4V×C −9 charges the integrator capacitor C t = OS + × OS − 300 10 sec (6) INT. As charge builds up on − 0.5×10 3A CINT, the output voltage of the integrator ramps downward towards ground. When the integrator output voltage (Pin 1) This simplifies into the timed period equation (see Equation 1). crosses the comparator threshold (–0.6 V) the comparator
COMPONENT SELECTION
triggers the one shot, whose time period, tOS is determined by the one-shot capacitor C Only four component values must be selected by the user. These OS. are input resistance RIN, timing capacitor COS, logic resistor R2, Specifically, the one-shot time period is and integration capacitor CINT. The first two determine the t = × input voltage and ful -scale frequency, while the last two are OS COS 6.8×103 sec/F + 3.0 10 7− × sec (1) determined by other circuit considerations. The reset period is initiated as soon as the integrator output Of the four components to be selected, R2 is the easiest to voltage crosses the comparator threshold, and the integrator define. As a pull-up resistor, it should be chosen to limit the ramps upward by an amount current through the output transistor to 8 mA if a TTL dV tOS V ∆ = t × = (1mA− maximum VOL of 0.4 V is desired. For example, if a 5 V logic OS IIN ) (2) dt C supply is used, R2 should be no smaller than 5 V/8 mA or INT 625 Ω. A larger value can be used if desired. After the reset period has ended, the device starts another integration period, as shown in Figure 8, and starts ramping RIN and COS are the only two parameters available to set the ful - downward again. The amount of time required to reach the scale frequency to accommodate the given signal range. The swing comparator threshold is given as variable that is affected by the choice of RIN and COS is nonlinearity. The selection guides of Figure 9 and Figure 10 show this quite tOS (1mA−I graphically. In general, larger values of C IN ) OS and lower full-scale ∆V C  1mA  T1 = = INT = t input currents (higher values of RIN) provide better linearity. In OS dV I  −1 (3) N  IIN  Figure 10, the implications of four different choices of RIN are dt CINT shown. Although the selection guide is set up for a unipolar configuration with a 0 V to 10 V input signal range, the results The output frequency is now given as can be extended to other configurations and input signal ranges. 1 I f IN = = = For a ful -scale frequency of 100 kHz (corresponding to 10 V OUT t + × input), among the available choices R OS T1 tOS 1mA IN = 20 kΩ and COS = 620 pF (4) F ×Hz V gives the lowest nonlinearity, 0.0038%. In addition, the highest IN / RIN 0.15 A C 11 − + × frequency that gives the 20 ppm minimum nonlinearity is OS 4.4 10 F approximately 33 kHz (40.2 kΩ and 1000 pF). Note that CINT, the integration capacitor, has no effect on the For input signal spans other than 10 V, the input resistance transfer relation, but merely determines the amplitude of the must be scaled proportionately. For example, if 100 kΩ is called sawtooth signal out of the integrator. out for a 0 V to 10 V span, 10 kΩ would be used with a 0 V to 1 V
One-Shot Timing
span, or 200 kΩ with a ±10 V bipolar connection. A key part of the preceding analysis is the one-shot time period The last component to be selected is the integration capacitor given in Equation 1. This time period can be broken down into CINT. In almost all cases, the best value for CINT can be calculated approximately 300 ns of propagation delay and a second time using the equation segment dependent linearly on timing capacitor COS. When the − one shot is triggered, a voltage switch that holds Pin 6 at analog 10 4 F /sec C = ( INT 1000 pF minimum) (7) ground is opened, al owing that voltage to change. An internal fMAX 0.5 mA current source connected to Pin 6 then draws its current out of C When the proper value for CINT is used, the charge balance OS, causing the voltage at Pin 6 to decrease linearly. At approximately –3.4 V, the one shot resets itself, architecture of the AD650 provides continuous integration thereby ending the timed period and starting the V/F of the input signal, therefore, large amounts of noise and conversion cycle over again. The total one-shot time period can interference can be rejected. If the output frequency is be written mathematical y as measured by counting pulses during a constant gate period, the integration provides infinite normal-mode rejection for V ∆ COS t = + frequencies corresponding to the gate period and its harmonics. OS GA T TE DELAY (5) IDISCHARGE However, if the integrator stage becomes saturated by an excessively large noise pulse, then the continuous integration of substituting actual values quoted in Equation 5, the signal is interrupted, allowing the noise to appear at the output. Rev. E | Page 8 of 20 Document Outline Features Functional Block Diagram Product Description Product Highlights Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Circuit Operation Unipolar Configuration One-Shot Timing Component Selection Bipolar V/F Unipolar V/F, Negative Input Voltage F/V Conversion High Frequency Operation Decoupling and Grounding Temperature Coefficients Nonlinearity Specification PSRR Other Circuit Considerations Applications Differential Voltage-to-Frequency Conversion Autozero Circuit Phase-Locked Loop F/V Conversion Outline Dimensions Ordering Guide