Datasheet ADXRS453 (Analog Devices) - 10

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Data Sheet ADXRS453 THEORY OF OPERATION
The ADXRS453 operates on the principle of a resonator gyroscope.
CONTINUOUS SELF-TEST
Figure 17 shows a simplified version of one of four polysilicon The ADXRS453 gyroscope implements a complete electro- sensing structures. Each sensing structure contains a dither frame mechanical self-test. An electrostatic force is applied to the that is electrostatically driven to resonance. This produces the gyroscope frame, resulting in a deflection of the capacitive sense necessary velocity element to produce a Coriolis force when the fingers. This deflection is exactly equivalent to deflection that device experiences angular rate. In the SOIC_CAV package, the occurs as a result of external rate input. The output from the ADXRS453 is designed to sense a z-axis (yaw) angular rate; the beam structure is processed by the same signal chain as a true LCC_V vertical mount package orients the device such that it rate output signal, providing complete coverage of both the can sense pitch or roll angular rate on the same PCB. electrical and mechanical components. The electromechanical self-test is performed continuously during operation at a rate higher than the output bandwidth of the device. The self-test routine generates equivalent positive and negative rate deflections. This information can then be filtered with no overall effect on the demodulated rate output.
X Y Z RATE SIGNAL WITH CONTINUOUS SELF-TEST SIGNAL. SELF-TEST AMPLITUDE. LOW FREQUENCY RATE INTERNALLY COMPARED INFORMATION.
19 0
TO THE SPECIFICATION
5- 018 915 5-
TABLE LIMITS.
0 915 0 Figure 18. Continuous Self-Test Demodulation Figure 17. Simplified Gyroscope Sensing Structure The difference amplitude between the positive and negative When the sensing structure is exposed to angular rate, the self-test deflections is filtered to f0/8000 (~1.95 Hz) and is resulting Coriolis force couples into an outer sense frame, continuously monitored and compared to hard-coded self-test which contains movable fingers that are placed between fixed limits. If the measured amplitude exceeds these limits (listed in pickoff fingers. This forms a capacitive pickoff structure that Table 1), one of two error conditions is asserted, depending on senses Coriolis motion. The resulting signal is fed to a series of the magnitude of the self-test error. gain and demodulation stages that produce the electrical rate For less severe self-test error magnitudes, the CST bit of the signal output. The quad sensor design rejects linear and angular fault register is asserted. However, the status bits (ST[1:0]) acceleration, including external g-forces and vibration. This is in the sensor data response remain set to 01 for valid achieved by mechanically coupling the four sensing structures sensor data. such that external g-forces appear as common-mode signals For more severe self-test errors, the CST bit of the fault that can be removed by the fully differential architecture register is asserted and the status bits (ST[1:0]) in the implemented in the ADXRS453. sensor data response are set to 00 for invalid sensor data. The resonator requires 22.5 V (typical) for operation. Because only 5 V is typically available in most applications, a switching Table 1 lists the thresholds for both of these failure conditions. regulator is included on chip. If desired, the user can access the self-test information by issuing a read command to the self-test memory register (Address 0x04). See the SPI Communication Protocol section for more informa- tion about error reporting. Rev. B | Page 9 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Mechanical Performance Noise Performance Applications Information Calibrated Performance Mechanical Considerations for Mounting Application Circuits ADXRS453 Signal Chain Timing SPI Communication Protocol Command/Response Device Data Latching SPI Timing Characteristics Command/Response Bit Definitions SQ2 to SQ0 Bits SM2 to SM0 Bits A8 to A0 Bits D15 to D0 Bits P Bit SPI Bit RE Bit DU Bit ST1 and ST0 Bits P0 Bit P1 Bit Fault Register Bit Definitions Fail Bit AMP Bit OV Bit UV Bit PLL Bit Q Bit NVM Bit POR Bit PWR Bit CST Bit CHK Bit Recommended Start-Up Sequence with CHK Bit Assertion Rate Data Format Memory Map and Registers Memory Map Memory Register Definitions Rate (RATEx) Registers Temperature (TEMx) Registers Low CST (LOCSTx) Registers High CST (HICSTx) Registers Quad Memory (QUADx) Registers Fault (FAULTx) Registers Part ID (PIDx) Registers Serial Number (SNx) Registers Package Orientation and Layout Information Solder Profile Package Marking Codes Outline Dimensions Ordering Guide