Datasheet ADXRS450 (Analog Devices) - 4

link to page 5 link to page 10 link to page 22 link to page 22 link to page 4 link to page 4 link to page 4 link to page 4
Data Sheet ADXRS450 SPECIFICATIONS
Specification conditions @ TA = TMIN to TMAX, PDD = 5 V, angular rate = 0°/sec, bandwidth = 80 Hz ±1 g, continuous self-test on.
Table 1. Parameter Test Conditions/Comments Symbol Min Typ Max Unit
MEASUREMENT RANGE Full-scale range FSR ±300 ±400 °/sec SENSITIVITY See Figure 2 Nominal Sensitivity 80 LSB/°/sec Sensitivity Tolerance ±3 % Nonlinearity1 Best fit straight line 0.05 0.25 % FSR rms Cross Axis Sensitivity2 ±3 % NULL Null Accuracy ±6 °/sec NOISE PERFORMANCE Rate Noise Density TA = 25°C 0.015 °/sec/√Hz LOW-PASS FILTER Cut-Off (−3 dB) Frequency f0/200 fLP 80 Hz Group Delay3 f = 0 Hz tLP 3.25 4 4.75 ms SHOCK AND VIBRATION IMMUNITY Sensitivity to Linear Acceleration DC to 5 kHz 0.03 °/sec/g Vibration Rectification 0.003 °/sec/g2 SELF TEST See Continuous Self-Test section Magnitude 2559 LSB Fault Register Threshold Compared to LOCST data 2239 2879 LSB Sensor Data Status Threshold Compared to LOCST data 1279 3839 LSB Frequency f0/32 fST 500 Hz ST Low-Pass Filter −3 dB Frequency f0/800 2 Hz Group Delay3 52 64 76 ms SPI COMMUNICATIONS Clock Frequency 8.08 MHz Voltage Input High MOSI, CS, SCLK 0.85 × PDD PDD + 0.3 V Voltage Input Low MOSI, CS, SCLK −0.3 PDD × 0.15 V Output Voltage Low MISO, current = 3 mA 0.5 V Output Voltage High MISO, current = −2 mA PDD − 0.5 V Pull-Up Current CS, PDD = 3.3 V, CS = 0.75 × PDD 50 200 µA CS, PDD = 5 V, CS = 0.75 × PDD 70 300 µA MEMORY REGISTERS See the Memory Register Definitions section Temperature Sensor Value at 45°C 0 LSB Scale Factor 5 LSB/°C Quad, ST, Rate, DNC Registers Scale Factor 80 LSB/°/sec POWER SUPPLY Supply Voltage PDD 3.15 5.25 V Quiescent Supply Current IDD 6.0 10.0 mA Turn-On Time Power on to 0.5°/sec of final 100 ms TEMPERATURE RANGE Independent of package type TMIN, TMAX −40 +105 °C 1 Maximum limit is guaranteed through Analog Devices, Inc., characterization. 2 Cross axis sensitivity specification does not include effects due to device mounting on a printed circuit board (PCB). 3 Minimum and maximum limits are guaranteed by design. Rev. C | Page 3 of 28 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Applications Information Mechanical Considerations for Mounting Applications Circuits ADXRS450 Signal Chain Timing SPI Communication Protocol Command/Response SPI Communications Characteristics SPI Applications Device Data Latching Command/Response—Bit Definitions SQ2 to SQ0 SM2 to SM0 A8 to A0 D15 to D0 SPI ST1 to ST0 P P0 P1 RE DU Fault Register Bit Definitions PLL Q NVM POR PWR CST CHK OV UV Fail Amp K-Bit Assertion: Recommended Start-Up Routine SPI Rate Data Format Memory Map and Registers Memory Map Memory Register Definitions Rate Registers Temperature (TEMx) Registers Low CST (LOCST) Memory Registers High CST (HICST) Memory Registers Quad Memory Registers Fault Registers Part ID (PID) Registers Serial Number (SN) Registers Dynamic Null Correction (DNC) Registers Package Orientation and Layout Information Package Marking Codes Outline Dimensions Ordering Guide