Datasheet ADXRS450 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | ±300°/sec High Vibration Immunity Digital Gyro |
| 页数 / 页 | 29 / 6 — Data Sheet. ADXRS450. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. 16 … |
| 修订版 | C |
| 文件格式/大小 | PDF / 696 Kb |
| 文件语言 | 英语 |
Data Sheet. ADXRS450. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. 16 SCLK. RSVD. 15 MOSI. 14 AVDD. 13 DV. TOP VIEW. MISO. (Not to Scale)
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Data Sheet ADXRS450 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DV 1 16 SCLK DD RSVD 2 15 MOSI RSVD 3 14 AVDD ADXRS450 CS 4 13 DV TOP VIEW SS MISO 5 (Not to Scale) 12 RSVD P 6 11 AV DD SS P 7 10 RSVD SS VX 8 9 CP5
003 08952- Figure 3. SOIC_CAV Pin Configuration
Table 4. 14-Lead SOIC_CAV Pin Function Descriptions Pin No. Mnemonic Description
1 DVDD Digital Regulated Voltage. See Figure 19 for the applications circuit diagram. 2 RSVD Reserved. This pin must be connected to DVSS. 3 RSVD Reserved. This pin must be connected to DVSS. 4 CS Chip Select. 5 MISO Master In/Slave Out. 6 PDD Supply Voltage. 7 PSS Switching Regulator Ground. 8 VX High Voltage Switching Node. See Figure 19 for the applications circuit diagram. 9 CP5 High Voltage Supply. See Figure 19 for the applications circuit diagram. 10 RSVD Reserved. This pin must be connected to DVSS. 11 AVSS Analog Ground. 12 RSVD Reserved. This pin must be connected to DVSS. 13 DVSS Digital Signal Ground. 14 AVDD Analog Regulated Voltage. See Figure 19 for the applications circuit diagram. 15 MOSI Master Out/Slave In. 16 SCLK SPI Clock. Rev. C | Page 5 of 28 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Applications Information Mechanical Considerations for Mounting Applications Circuits ADXRS450 Signal Chain Timing SPI Communication Protocol Command/Response SPI Communications Characteristics SPI Applications Device Data Latching Command/Response—Bit Definitions SQ2 to SQ0 SM2 to SM0 A8 to A0 D15 to D0 SPI ST1 to ST0 P P0 P1 RE DU Fault Register Bit Definitions PLL Q NVM POR PWR CST CHK OV UV Fail Amp K-Bit Assertion: Recommended Start-Up Routine SPI Rate Data Format Memory Map and Registers Memory Map Memory Register Definitions Rate Registers Temperature (TEMx) Registers Low CST (LOCST) Memory Registers High CST (HICST) Memory Registers Quad Memory Registers Fault Registers Part ID (PID) Registers Serial Number (SN) Registers Dynamic Null Correction (DNC) Registers Package Orientation and Layout Information Package Marking Codes Outline Dimensions Ordering Guide
Data Sheet ADXRS450 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DV 1 16 SCLK DD RSVD 2 15 MOSI RSVD 3 14 AVDD ADXRS450 CS 4 13 DV TOP VIEW SS MISO 5 (Not to Scale) 12 RSVD P 6 11 AV DD SS P 7 10 RSVD SS VX 8 9 CP5
003 08952- Figure 3. SOIC_CAV Pin Configuration
Table 4. 14-Lead SOIC_CAV Pin Function Descriptions Pin No. Mnemonic Description
1 DVDD Digital Regulated Voltage. See Figure 19 for the applications circuit diagram. 2 RSVD Reserved. This pin must be connected to DVSS. 3 RSVD Reserved. This pin must be connected to DVSS. 4 CS Chip Select. 5 MISO Master In/Slave Out. 6 PDD Supply Voltage. 7 PSS Switching Regulator Ground. 8 VX High Voltage Switching Node. See Figure 19 for the applications circuit diagram. 9 CP5 High Voltage Supply. See Figure 19 for the applications circuit diagram. 10 RSVD Reserved. This pin must be connected to DVSS. 11 AVSS Analog Ground. 12 RSVD Reserved. This pin must be connected to DVSS. 13 DVSS Digital Signal Ground. 14 AVDD Analog Regulated Voltage. See Figure 19 for the applications circuit diagram. 15 MOSI Master Out/Slave In. 16 SCLK SPI Clock. Rev. C | Page 5 of 28 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Applications Information Mechanical Considerations for Mounting Applications Circuits ADXRS450 Signal Chain Timing SPI Communication Protocol Command/Response SPI Communications Characteristics SPI Applications Device Data Latching Command/Response—Bit Definitions SQ2 to SQ0 SM2 to SM0 A8 to A0 D15 to D0 SPI ST1 to ST0 P P0 P1 RE DU Fault Register Bit Definitions PLL Q NVM POR PWR CST CHK OV UV Fail Amp K-Bit Assertion: Recommended Start-Up Routine SPI Rate Data Format Memory Map and Registers Memory Map Memory Register Definitions Rate Registers Temperature (TEMx) Registers Low CST (LOCST) Memory Registers High CST (HICST) Memory Registers Quad Memory Registers Fault Registers Part ID (PID) Registers Serial Number (SN) Registers Dynamic Null Correction (DNC) Registers Package Orientation and Layout Information Package Marking Codes Outline Dimensions Ordering Guide