Datasheet ADIS16060 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | Wide Bandwidth Yaw Rate Gyroscope with SPI |
| 页数 / 页 | 13 / 6 — Data Sheet. ADIS16060. TIMING SPECIFICATIONS. Table 2. Read/Output … |
| 修订版 | A |
| 文件格式/大小 | PDF / 309 Kb |
| 文件语言 | 英语 |
Data Sheet. ADIS16060. TIMING SPECIFICATIONS. Table 2. Read/Output Sequence Parameter Figure. Reference. Symbol. Min. Typ. Max. Unit
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Data Sheet ADIS16060 TIMING SPECIFICATIONS
TA = 25°C, angular rate = 0°/sec, unless otherwise noted.1
Table 2. Read/Output Sequence Parameter Figure Reference Symbol Min Typ Max Unit
Serial Clock Frequency 2.9 MHz Throughput Rate See Figure 2 tCYC 100 kHz MSEL1 Falling to SCLK Low See Figure 2 tCSD 0 μs MSEL1 Falling to SCLK Rising See Figure 2 tSUCS 20 ns SLCK Falling to Data Remains Valid See Figure 2 tHDO 5 16 ns MSEL1 Rising Edge to DOUT High Impedance See Figure 2 tDIS 14 100 ns SCLK Falling to Data Valid See Figure 2 tEN 16 50 ns Acquisition Time See Figure 2 tACQ 400 ns DOUT Fall Time See Figure 2 tF 11 25 ns DOUT Rise Time See Figure 2 tR 11 25 ns Data Setup Time See Figure 3 t5 5 5 ns SCLK Falling Edge to MSEL2 Rising Edge See Figure 3 t7 0 0 ns Data Hold Time See Figure 3 t6 4.5 ns 1 Guaranteed by design. All input signals are specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
Timing Diagrams tCYC COMPLETE CYCLE MSEL1 tSUCS tACQ POWER DOWN SCLK 1 4 5 t t CSD EN tHDO tDIS HIGH-Z HIGH-Z DOUT 0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 (MSB) (LSB)
-002
NOTE: A MINIMUM OF 20 CLOCK CYCLES ARE REQUIRED FOR 14-BIT CONVERSION.
07103 Figure 2. Serial Interface Timing Diagram—Read/Output Sequence (CPOL = 0, CPHA = 0)
t7 t MSEL2 5 t6 SCLK DIN DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
03 0
NOTE:
3-
THE LAST EIGHT BITS CLOCKED IN ARE LATCHED WITH THE RISING EDGE OF THE MSEL2 LINE.
0710 Figure 3. Serial Interface Timing—Input/Configuration Sequence (CPOL = 0, CPHA = 1) Rev. A | Page 5 of 12 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Analog-to-Digital Converter Input Rate Sensitive Axis Basic Operation Serial Peripheral Interface (SPI) Selecting Output Data Output Data Access Output Data Formatting ADC Conversion Applications Information Supply And Common Considerations Setting Bandwidth Increasing Measurement Range Dynamic Digital Sensitivity Scaling Temperature Measurements Self-Test Function Outline Dimensions Ordering Guide
Data Sheet ADIS16060 TIMING SPECIFICATIONS
TA = 25°C, angular rate = 0°/sec, unless otherwise noted.1
Table 2. Read/Output Sequence Parameter Figure Reference Symbol Min Typ Max Unit
Serial Clock Frequency 2.9 MHz Throughput Rate See Figure 2 tCYC 100 kHz MSEL1 Falling to SCLK Low See Figure 2 tCSD 0 μs MSEL1 Falling to SCLK Rising See Figure 2 tSUCS 20 ns SLCK Falling to Data Remains Valid See Figure 2 tHDO 5 16 ns MSEL1 Rising Edge to DOUT High Impedance See Figure 2 tDIS 14 100 ns SCLK Falling to Data Valid See Figure 2 tEN 16 50 ns Acquisition Time See Figure 2 tACQ 400 ns DOUT Fall Time See Figure 2 tF 11 25 ns DOUT Rise Time See Figure 2 tR 11 25 ns Data Setup Time See Figure 3 t5 5 5 ns SCLK Falling Edge to MSEL2 Rising Edge See Figure 3 t7 0 0 ns Data Hold Time See Figure 3 t6 4.5 ns 1 Guaranteed by design. All input signals are specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
Timing Diagrams tCYC COMPLETE CYCLE MSEL1 tSUCS tACQ POWER DOWN SCLK 1 4 5 t t CSD EN tHDO tDIS HIGH-Z HIGH-Z DOUT 0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 (MSB) (LSB)
-002
NOTE: A MINIMUM OF 20 CLOCK CYCLES ARE REQUIRED FOR 14-BIT CONVERSION.
07103 Figure 2. Serial Interface Timing Diagram—Read/Output Sequence (CPOL = 0, CPHA = 0)
t7 t MSEL2 5 t6 SCLK DIN DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
03 0
NOTE:
3-
THE LAST EIGHT BITS CLOCKED IN ARE LATCHED WITH THE RISING EDGE OF THE MSEL2 LINE.
0710 Figure 3. Serial Interface Timing—Input/Configuration Sequence (CPOL = 0, CPHA = 1) Rev. A | Page 5 of 12 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Analog-to-Digital Converter Input Rate Sensitive Axis Basic Operation Serial Peripheral Interface (SPI) Selecting Output Data Output Data Access Output Data Formatting ADC Conversion Applications Information Supply And Common Considerations Setting Bandwidth Increasing Measurement Range Dynamic Digital Sensitivity Scaling Temperature Measurements Self-Test Function Outline Dimensions Ordering Guide