Datasheet AD8450 (Analog Devices) - 9

AD8450 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. THERMAL RESISTANCE Parameter Rating
The θJA value assumes a 4-layer JEDEC standard board with Analog Supply Voltage (AVCC − AVEE) 36 V zero airflow. Digital Supply Voltage (DVCC − DGND) 36 V Maximum Voltage at Input Pins (ISVP, ISVN, AVEE + 55 V
Table 3. Thermal Resistance
BVPx, and BVNx)
Package Type θJA Unit
Minimum Voltage at Input Pins (ISVP, ISVN, BVPx, AVCC − 55 V 80-Lead LQFP 54.7 °C/W and BVNx) Maximum Voltage at All Input Pins, Except ISVP, AVCC ISVN, BVPx, and BVNx
ESD CAUTION
Minimum Voltage at All Input Pins, Except ISVP, AVEE ISVN, BVPx, and BVNx Maximum Digital Supply Voltage with Respect +0.5 V to the Positive Analog Supply (DVCC − AVCC) Minimum Digital Supply Voltage with Respect to −0.5 V the Negative Analog Supply (DVCC − AVEE) Maximum Digital Ground with Respect to the +0.5 V Positive Analog Supply (DGND − AVCC) Minimum Digital Ground with Respect to the −0.5 V Negative Analog Supply (DGND − AVEE) Maximum Analog Ground with Respect to the +0.5 V Positive Analog Supply (AGND − AVCC) Minimum Analog Ground with Respect to the −0.5 V Negative Analog Supply (AGND − AVEE) Maximum Analog Ground with Respect to the +0.5 V Digital Ground (AGND − DGND) Minimum Analog Ground with Respect to the −0.5 V Digital Ground (AGND − DGND) Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 8 of 41 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS PGIA CHARACTERISTICS PGDA CHARACTERISTICS CC AND CV LOOP FILTER AMPLIFIERS, UNCOMMITTED OP AMP, AND VSET BUFFER VINT BUFFER CURRENT SHARING AMPLIFIER COMPARATORS REFERENCE CHARACTERISTICS THEORY OF OPERATION INTRODUCTION PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER (PGIA) Gain Selection Reversing Polarity When Charging and Discharging PGIA Offset Option Battery Reversal and Overvoltage Protection PROGRAMMABLE GAIN DIFFERENCE AMPLIFIER (PGDA) CC AND CV LOOP FILTER AMPLIFIERS COMPENSATION VINT BUFFER MODE PIN, CHARGE AND DISCHARGE CONTROL OVERCURRENT AND OVERVOLTAGE COMPARATORS CURRENT SHARING BUS AND IMAX OUTPUT APPLICATIONS INFORMATION FUNCTIONAL DESCRIPTION POWER SUPPLY CONNECTIONS POWER SUPPLY SEQUENCING POWER-ON SEQUENCE POWER-OFF SEQUENCE PGIA CONNECTIONS Current Sensors Optional Low-Pass Filter PGDA CONNECTIONS Reverse Battery Conditions BATTERY CURRENT AND VOLTAGE CONTROL INPUTS (ISET AND VSET) LOOP FILTER AMPLIFIERS CONNECTING TO A PWM CONTROLLER (VCTRL PIN) OVERVOLTAGE AND OVERCURRENT COMPARATORS STEP BY STEP DESIGN EXAMPLE Step 1: Design the Switching Power Converter Step 2: Identify the Control Voltage Range of the ADP1972 Step 3: Determine the Control Voltage for the CV Loop and the PGDA Gain Step 4: Determine the Control Voltage for the CC Loop, the Shunt Resistor, and the PGIA Gain Step 5: Choose the Control Voltage Sources Step 6: Select the Compensation Devices ADDITIONAL INFORMATION EVALUATION BOARD INTRODUCTION FEATURES AND TESTS TESTING THE AD8450-EVALZ PGIA and Offset PGIA Gain Test PGIA in an Application Simple Offset Test Offset in an Application PGDA and Offset Simple Test PGDA in an Application PGDA Offset Overload Comparators VSET Buffer CV and CC Loop Filter Amplifiers CC and CV Integrator Tests Uncommitted Op Amp USING THE AD8450 SCHEMATIC AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE