Datasheet KSZ8765CLX (Microchip) - 8

KSZ8765CLX TABLE 2-1: SIGNALS - KSZ8765CLX (CONTINUED) Pin Pin Type Port Description Number Name Note 2-1
26 VDD12D P — 1.2V Core Power. 27 GNDD GND — Digital Ground. 28 LED4_1 Ipu/O 4 Port 4 LED Indicator 1: See Global Register 11 bits [5:4] for details. 29 TXEN5/ Ipd 5 GMII/MII/RMII: Port 5 Switch transmit enable. TXD5_CTL RGMII: Transmit data control. 30 TXD5_0 Ipd 5 GMII/RGMII/MII/RMII: Port 5 switch transmit Bit[0]. 31 LED4_0 Ipu/O 4 Port 4 LED Indicator 0: See Global Register 11 bits [5:4] for details. 32 TXD5_1 Ipd 5 GMII/RGMII/MII/RMII: Port 5 switch transmit Bit[1]. 33 GNDD GND — Digital Ground. 34 VDDIO P — 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry. 35 TXD5_2 Ipd 5 GMII/RGMII/MII: Port 5 switch transmit Bit[2]. RMII: No connection. 36 TXD5_3 Ipd 5 GMII/RGMII/MII: Port 5 switch transmit Bit[3]. RMII: No connection. 37 TXER5 Ipd 5 GMII/MII: Port 5 switch transmit error. RGMII/RMII: No connection. 38 TXD5_4 Ipd 5 GMII: Port 5 switch transmit Bit[4]. RGMII/MII/RMII: No connection. 39 TXD5_5 Ipd 5 GMII: Port 5 switch transmit Bit[5]. RGMII/MII/RMII: No connection. 40 TXD5_6 Ipd 5 GMII: Port 5 switch transmit Bit[6]. RGMII/MII/RMII: No connection. 41 TXD5_7 Ipd 5 GMII: Port 5 Switch transmit Bit[7]. RGMII/MII/RMII: No connection. 42 VDD12D P — 1.2V Core Power. 43 TXC5/ I/O 5 Port 5 Switch GMAC5 Clock Pin: REFCLKI/ MII: 2.5/25 MHz clock, PHY mode is output, MAC mode is input. GTXC5 RMII: Input for receiving 50 MHz clock in normal mode GMII: Input 125 MHz clock for the transmit RGMII: Input 125 MHz clock with falling and rising edge to latch data for the transmit. 44 RXC5/ I/O 5 Port 5 Switch GMAC5 Clock Pin: GRXC5 MII: 2.5/25 MHz clock, PHY mode is output, MAC mode is input. RMII: Output 50 MHz reference clock for the receiving/transmit in the clock mode. GMII: Output 125 MHz clock for the receiving. RGMII: Output 125 MHz clock with falling and rising edge to latch data for the receiving. DS00002130A-page 8  2016 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines