Datasheet LTC2500-32 (Analog Devices) - 7

LTC2500-32
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tHSDOA SDOA Data Remains Valid Delay from CL = 20pF (Note 12) l 1 ns SCKA tDSDOADRLL SDOA Data Valid Delay from DRL CL = 20pF (Note 12) l 5 ns tENA Bus Enable Time After RDLA (Note 13) l 16 ns tDISA Bus Relinquish Time After RDLA (Note 13) l 13 ns tSCKB SCKB Period (Notes 13, 14) l 10 ns tSCKBH SCKB High Time l 4 ns tSCKBL SCKB Low Time l 4 ns tDSDOB SDOB Data Valid Delay from SCKB CL = 20pF, OVDD = 5.25V l 8.5 ns CL = 20pF, OVDD = 2.5V l 8.5 ns CL = 20pF, OVDD = 1.71V l 9.5 ns tHSDOB SDOB Data Remains Valid Delay from CL = 20pF (Note 12) l 1 ns SCKB tDSDOBBUSYL SDOB Data Valid Delay from BUSY CL = 20pF (Note 12) l 5 ns tENB Bus Enable Time After RDLB (Note 13) l 16 ns tDISB Bus Relinquish Time After RDLB (Note 13) l 13 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 8:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute straight line passing through the actual endpoints of the transfer curve. Maximum Rating condition for extended periods may affect device The deviation is measured from the center of the quantization band. reliability and lifetime.
Note 9:
Bipolar zero-scale error is the offset voltage measured from
Note 2:
All voltage values are with respect to ground. –0.5LSB when the output code flickers between 0000 0000 0000 0000
Note 3:
When these pin voltages are taken below ground or above REF or 0000 0000 0000 0000 and 1111 1111 1111 1111 1111 1111 1111 OVDD, they will be clamped by internal diodes. This product can handle 1111. Full-scale bipolar error is the worst-case of –FS or +FS untrimmed input currents up to 100mA below ground or above REF or OVDD without deviation from ideal first and last code transitions and includes the effect latchup. of offset error.
Note 4:
VDD = 2.5V, OVDD = 2.5V, REF = 5V, VCM = 2.5V, fSMPL = 1MHz.
Note 10:
All specifications in dB are referred to a full-scale ±5V input with
Note 5:
Recommended operating conditions. a 5V reference voltage.
Note 6:
Transition noise is defined as the noise level of the ADC with IN+
Note 11:
fSMPL = 1MHz, IREF varies proportionally with sample rate. and IN– shorted.
Note 12:
Guaranteed by design, not subject to test.
Note 7:
The DC specifications at SDOA are measured and guaranteed at
Note 13:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V SDOB. The operation of the digital filters is tested separately to guarantee and OVDD = 5.25V. the same DC specifications at SDOA.
Note 14:
tSCKA, tSCKB of 10ns maximum allows a shift clock frequency up to 100MHz for rising edge capture. 0.8 • OV t DD WIDTH 0.2 • OVDD 50% 50% tDELAY tDELAY 250032 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
Figure 1. Voltage Levels for Timing Specifications
250032fb For more information www.linear.com/LTC2500-32 7 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics for Filtered Output (SDOA) Dynamic Accuracy for Filtered Output (SDOA) Converter Characteristics for No latency Output (SDOB) Dynamic Accuracy for No Latency Output (SDOB) Reference Input Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Overview Converter Operation Transfer Function Analog Input Input Drive Circuits ADC Reference Dynamic Performance Power Considerations Timing and Control Decimation Filters Digital Filter Types Digital Interface Preset Filter Modes Filtered Output Data No Latency Output Data Board Layout Package Description Revision History Typical Application Related Parts