Datasheet LTC2512-24 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 24-Bit Over-Sampling ADC with Configurable Flat Passband Digital Filter |
| 页数 / 页 | 38 / 5 — The. denotes the specifications which apply over the full operating … |
| 文件格式/大小 | PDF / 709 Kb |
| 文件语言 | 英语 |
The. denotes the specifications which apply over the full operating temperature
该数据表的模型线
文件文字版本
LTC2512-24 POWER REQUIREMENTS
The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage l 2.375 2.5 2.625 V OVDD Supply Voltage l 1.71 5.25 V IVDD Supply Current 1.6Msps Sample Rate l 12 16 mA IOVDD Supply Current 1.6Msps Sample Rate (CL = 20pF) 0.4 mA IPD Power Down Mode Conversion Done (IVDD + IOVDD + IREF) l 1 350 µA PD Power Dissipation 1.6Msps Sample Rate (IVDD) 30 40 mW Power Down Mode Conversion Done (IVDD + IOVDD + IREF) 2.5 875 µW ADC TIMING CHARACTERISTICS
The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency (Note 12) l 1.6 Msps fDRA Output Data Rate at SDOA l 400 ksps fDRB Output Data Rate at SDOB (Note 12) l 1.6 Msps tCONV Conversion Time l 405 460 ns tACQ Acquisition Time tACQ = tCYC – tCONV – tBUSYLH (Note 8) l 152 ns tCYC Time Between Conversions l 625 ns tMCLKH MCLK High Time l 20 ns tMCLKL Minimum Low Time for MCLK (Note 13) l 20 ns tBUSYLH MCLK↑ to BUSY↑ Delay CL = 20pF l 13 ns tDRLLH MCLK↑ to DRL↑ Delay CL = 20pF l 18 ns tQUIET SCKA, SCKB Quiet Time from MCLK↑ (Note 8) l 10 ns tSCKA SCKA Period (Notes 13, 14) l 10 ns tSCKAH SCKA High Time l 4 ns tSCKAL SCKA Low Time l 4 ns tDSDOA SDOA Data Valid Delay from SCKA↑ CL = 20pF, OVDD = 5.25V l 8.5 ns CL = 20pF, OVDD = 2.5V l 8.5 ns CL = 20pF, OVDD = 1.71V l 9.5 ns tHSDOA SDOA Data Remains Valid Delay from SCKA↑ CL = 20pF (Note 8) l 1 ns tDSDOADRLL SDOA Data Valid Delay from DRL↓ CL = 20pF (Note 8) l 5 ns tENAA Bus Enable Time After RDLA↓ (Note 13) l 16 ns tDISA Bus Relinquish Time After RDLA↑ (Note 13) l 13 ns tSCKB SCKB Period (Notes 13, 14) l 10 ns tSCKBH SCKB High Time l 4 ns tSCKBL SCKB Low Time l 4 ns tDSDOB SDOB Data Valid Delay from SCKB↑ CL = 20pF, OVDD = 5.25V l 8.5 ns CL = 20pF, OVDD = 2.5V l 8.5 ns CL = 20pF, OVDD = 1.71V l 9.5 ns tHSDOB SDOB Data Remains Valid Delay from SCKB↑ CL = 20pF (Note 8) l 1 ns 251224fa For more information www.linear.com/LTC2512-24 5
The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage l 2.375 2.5 2.625 V OVDD Supply Voltage l 1.71 5.25 V IVDD Supply Current 1.6Msps Sample Rate l 12 16 mA IOVDD Supply Current 1.6Msps Sample Rate (CL = 20pF) 0.4 mA IPD Power Down Mode Conversion Done (IVDD + IOVDD + IREF) l 1 350 µA PD Power Dissipation 1.6Msps Sample Rate (IVDD) 30 40 mW Power Down Mode Conversion Done (IVDD + IOVDD + IREF) 2.5 875 µW ADC TIMING CHARACTERISTICS
The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency (Note 12) l 1.6 Msps fDRA Output Data Rate at SDOA l 400 ksps fDRB Output Data Rate at SDOB (Note 12) l 1.6 Msps tCONV Conversion Time l 405 460 ns tACQ Acquisition Time tACQ = tCYC – tCONV – tBUSYLH (Note 8) l 152 ns tCYC Time Between Conversions l 625 ns tMCLKH MCLK High Time l 20 ns tMCLKL Minimum Low Time for MCLK (Note 13) l 20 ns tBUSYLH MCLK↑ to BUSY↑ Delay CL = 20pF l 13 ns tDRLLH MCLK↑ to DRL↑ Delay CL = 20pF l 18 ns tQUIET SCKA, SCKB Quiet Time from MCLK↑ (Note 8) l 10 ns tSCKA SCKA Period (Notes 13, 14) l 10 ns tSCKAH SCKA High Time l 4 ns tSCKAL SCKA Low Time l 4 ns tDSDOA SDOA Data Valid Delay from SCKA↑ CL = 20pF, OVDD = 5.25V l 8.5 ns CL = 20pF, OVDD = 2.5V l 8.5 ns CL = 20pF, OVDD = 1.71V l 9.5 ns tHSDOA SDOA Data Remains Valid Delay from SCKA↑ CL = 20pF (Note 8) l 1 ns tDSDOADRLL SDOA Data Valid Delay from DRL↓ CL = 20pF (Note 8) l 5 ns tENAA Bus Enable Time After RDLA↓ (Note 13) l 16 ns tDISA Bus Relinquish Time After RDLA↑ (Note 13) l 13 ns tSCKB SCKB Period (Notes 13, 14) l 10 ns tSCKBH SCKB High Time l 4 ns tSCKBL SCKB Low Time l 4 ns tDSDOB SDOB Data Valid Delay from SCKB↑ CL = 20pF, OVDD = 5.25V l 8.5 ns CL = 20pF, OVDD = 2.5V l 8.5 ns CL = 20pF, OVDD = 1.71V l 9.5 ns tHSDOB SDOB Data Remains Valid Delay from SCKB↑ CL = 20pF (Note 8) l 1 ns 251224fa For more information www.linear.com/LTC2512-24 5