Datasheet AD420 (Analog Devices) - 6

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AD420 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NC 1 24 NC VLL 2 23 VCC FAULT DETECT 3 22 NC RANGE SELECT 2 4 21 CAP 2 RANGE SELECT 1 5 AD420 20 CAP 1 CLEAR 6 TOP VIEW 19 BOOST (Not to Scale) LATCH 7 18 IOUT CLOCK 8 17 VOUT DATA IN 9 16 OFFSET TRIM DATA OUT 10 15 REF IN GND 11 14 REF OUT NC 12 13 NC
002
NC = NO CONNECT
00494- Figure 2. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Function
1, 12, NC No Connection. No internal connections inside device. 13, 24 2 VLL Auxiliary buffered +4.5 V digital logic voltage. This pin is the internal supply voltage for the digital circuitry and can be used as a termination for pull-up resistors. An external +5 V power supply can be connected to VLL. It will override this buffered voltage, thus reducing the internal power dissipation. The VLL pin should be decoupled to GND with a 0.1 µF capacitor. See the Power Supplies and Decoupling section. 3 FAULT DETECT FAULT DETECT, connected to a pull-up resistor, is asserted low when the output current does not match the DAC’s programmed value, for example, in case the current loop is broken. 4 RANGE SELECT 2 Selects the converter’s output operating range. One output voltage range and three 5 RANGE SELECT 1 output current ranges are available. 6 CLEAR Valid VIH unconditionally forces the output to go to the minimum of its programmed range. After CLEAR is removed the DAC output will remain at this value. The data in the input register is unaffected. 7 LATCH In the 3-wire interface mode a rising edge parallel loads the serial input register data into the DAC. To use the asynchronous mode connect LATCH through a current limiting resistor to VCC. 8 CLOCK Data Clock Input. The clock period is equal to the input data bit rate in the 3-wire interface mode and is 16 times the bit rate in asynchronous mode. 9 DATA IN Serial Data Input. 10 DATA OUT Serial Data Output. In the 3-wire interface mode, this output can be used for daisy-chaining multiple AD420s. In the asynchronous mode a positive pulse will indicate a framing error after the stop-bit is received. 11 GND Ground (Common). 14 REF OUT +5 V Reference Output. 15 REF IN Reference Input. 16 OFFSET TRIM Offset Adjust. 17 VOUT Voltage Output. 18 IOUT Current Output. 19 BOOST Connect to an external transistor to reduce the power dissipated in the AD420 output transistor, if desired. 20 CAP 1 These pins are used for internal filtering. Connect capacitors between each of these 21 CAP 2 pins and VCC. Refer to the description of current output operation. 22 NC No Connection. Do not connect anything to this pin. 23 VCC Power Supply Input. The VCC pin should always be decoupled to GND with a 0.1 µF capacitor. See the Power Supplies and Decoupling section. Rev. I | Page 6 of 16 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TIMING REQUIREMENTS THREE-WIRE INTERFACE THREE-WIRE INTERFACE FAST EDGES ON DIGITAL INPUT ASYNCHRONOUS INTERFACE TERMINOLOGY THEORY OF OPERATION APPLICATIONS INFORMATION CURRENT OUTPUT DRIVING INDUCTIVE LOADS VOLTAGE-MODE OUTPUT OPTIONAL SPAN AND ZERO TRIM THREE-WIRE INTERFACE USING MULTIPLE DACS WITH FAULT DETECT ASYNCHRONOUS INTERFACE USING OPTOCOUPLERS MICROPROCESSOR INTERFACE AD420-TO-MC68HC11 (SPI BUS) INTERFACE AD420 TO MICROWIRE INTERFACE EXTERNAL BOOST FUNCTION AD420 PROTECTION TRANSIENT VOLTAGE PROTECTION BOARD LAYOUT AND GROUNDING POWER SUPPLIES AND DECOUPLING OUTLINE DIMENSIONS ORDERING GUIDE