Datasheet AD420 (Analog Devices) - 7

Data Sheet AD420 TIMING REQUIREMENTS
TA = −40°C to +85°C, VCC = +12 V to +32 V.
CLOCK THREE-WIRE INTERFACE DATA IN 0 1 0 0 1 CLOCK T T 5 4 3 1 0 T T T R 1 1 1 IT T OP R A BI T T T BI EXT BI A BI WORD “N” WORD “N + 1” BI BI BI B ST N ST ST TO DATA IN 1 0 1 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 0 1 (INTERNALLY GENERATED LATCH) ) ) 1 B B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B15 B14 B13 B12 B1 B10 S B15 B14 B13 B12 (MSB (L EXPANDED TIME VIEW BELOW LATCH CLOCK COUNTER STARTS HERE CONFIRM START BIT SAMPLE BIT 15 WORD “N – 1” WORD “N” DATA OUT 1 0 1 1 CLOCK 5 4 3 2 0 1 2 8 16 24 tCK B1 B1 B1 B1 t DATA IN START BIT DATA BIT 15 BIT 14 CL CLOCK tCH tDH t EXPANDED TIME VIEW BELOW DS tACK DATA IN tACL CLOCK tDW tACH tLD tADS tADH t LATCH LL tADW t
04
LH
0 4-
DATA IN t
49
SD
00 3 -00
DATA OUT
4 Figure 4. Timing Diagram for Asynchronous Interface 49 00 Figure 3. Timing Diagram for 3-Wire Interface
Table 6. Timing Specifications for Asynchronous Interface Parameter Label Limit Units Table 5. Timing Specification for 3-Wire Interface
Asynchronous Clock Period tACK 400 ns min
Parameter Label Limit Units
Asynchronous Clock Low Time tACL 50 ns min Data Clock Period tCK 300 ns min Asynchronous Clock High Time tACH 150 ns min Data Clock Low Time tCL 80 ns min Data Stable Width (Critical Clock Edge) tADW 300 ns min Data Clock High Time tCH 80 ns min Data Setup Time (Critical Clock Edge) tADS 60 ns min Data Stable Width tDW 125 ns min Data Hold Time (Critical Clock Edge) tADH 20 ns min Data Setup Time tDS 40 ns min Clear Pulse Width tCLR 50 ns min Data Hold Time tDH 5 ns min Latch Delay Time t
ASYNCHRONOUS INTERFACE
LD 80 ns min Latch Low Time tLL 80 ns min Note that in the timing diagram for asynchronous mode oper- Latch High Time tLH 80 ns min ation each data word is framed by a START (0) bit and a STOP Serial Output Delay Time tSD 225 ns max (1) bit. The data timing is with respect to the rising edge of the Clear Pulse Width tCLR 50 ns min CLOCK at the center of each bit cell. Bit cells are 16 clocks
THREE-WIRE INTERFACE FAST EDGES ON DIGITAL
long, and the first cell (the START bit) begins at the first clock
INPUT
following the leading (falling) edge of the START bit. Thus, the MSB (D15) is sampled 24 clock cycles after the beginning of With a fast rising edge (<100 ns) on one of the serial inputs the START bit, D14 is sampled at clock number 40, and so on. (CLOCK, DATA IN, LATCH) while another input is logic high, During any dead time before writing the next word the DATA the part may be triggered into a test mode and the contents of IN pin must remain at Logic 1. the data register may become corrupted, which may result in the output being loaded with an incorrect value. If fast edges are The DAC output updates when the STOP bit is received. In expected on the digital input lines, it is recommended that the the case of a framing error (the STOP bit sampled as a 0) the latch line remain at Logic 0 during serial loading of the DAC. AD420 will output a pulse at the DATA OUT pin one clock Similarly, the clock line should remain low during updates of period wide during the clock period subsequent to sampling the DAC via the latch pin. Alternatively, the addition of small the STOP bit. The DAC output will not update if a framing value capacitors on the digital lines will slow down the edge. error is detected. Rev. I | Page 7 of 16 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TIMING REQUIREMENTS THREE-WIRE INTERFACE THREE-WIRE INTERFACE FAST EDGES ON DIGITAL INPUT ASYNCHRONOUS INTERFACE TERMINOLOGY THEORY OF OPERATION APPLICATIONS INFORMATION CURRENT OUTPUT DRIVING INDUCTIVE LOADS VOLTAGE-MODE OUTPUT OPTIONAL SPAN AND ZERO TRIM THREE-WIRE INTERFACE USING MULTIPLE DACS WITH FAULT DETECT ASYNCHRONOUS INTERFACE USING OPTOCOUPLERS MICROPROCESSOR INTERFACE AD420-TO-MC68HC11 (SPI BUS) INTERFACE AD420 TO MICROWIRE INTERFACE EXTERNAL BOOST FUNCTION AD420 PROTECTION TRANSIENT VOLTAGE PROTECTION BOARD LAYOUT AND GROUNDING POWER SUPPLIES AND DECOUPLING OUTLINE DIMENSIONS ORDERING GUIDE