Datasheet MC74VHC1GT50 (ON Semiconductor)
| 制造商 | ON Semiconductor |
| 描述 | Noninverting Buffer / CMOS Logic Level Shifter |
| 页数 / 页 | 6 / 1 — TTL−Compatible Inputs. www.onsemi.com. MARKING. DIAGRAMS. SC−88A / … |
| 修订版 | 16 |
| 文件格式/大小 | PDF / 79 Kb |
| 文件语言 | 英语 |
TTL−Compatible Inputs. www.onsemi.com. MARKING. DIAGRAMS. SC−88A / SOT−353 / SC−70. DF SUFFIX. CASE 419A. TSOP−5 / SOT−23 / SC−59
该数据表的模型线
文件文字版本
link to page 4 MC74VHC1GT50 Noninverting Buffer / CMOS Logic Level Shifter
TTL−Compatible Inputs
The MC74VHC1GT50 is a single gate noninverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
www.onsemi.com
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.
MARKING
The device input is compatible with TTL−type input thresholds and
DIAGRAMS
the output has a full 5 V CMOS level output swing. The input protection 5 5 circuitry on this device allows overvoltage tolerance on the input, M allowing the device to be used as a logic−level translator from 3 V 1 VL M G G CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
SC−88A / SOT−353 / SC−70
CMOS Logic while operating at the high−voltage power supply.
DF SUFFIX
1 The MC74VHC1GT50 input structure provides protection when
CASE 419A
voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74VHC1GT50 to be used to interface high voltage to 5 low voltage circuits. The output structures also provide protection 5 VL M G when VCC = 0 V. These input and output structures help prevent G device destruction caused by supply voltage − input/output voltage 1 1 mismatch, battery backup, hot insertion, etc.
TSOP−5 / SOT−23 / SC−59 DT SUFFIX Features
•
CASE 483
Designed for 1.65 V to 5.5 VCC Operation • High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V VL = Device Code • Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C M = Date Code* • G = Pb−Free Package TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V, VCC = 5 V • (Note: Microdot may be in either location) CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load *Date Code orientation and/or position may vary • Power Down Protection Provided on Inputs and Outputs depending upon manufacturing location. • Balanced Propagation Delays • Pin and Function Compatible with Other Standard Logic Families • Chip Complexity: FETs = 104; Equivalent Gates = 26
PIN ASSIGNMENT
• NLV Prefix for Automotive and Other Applications Requiring 1 NC Unique Site and Control Change Requirements; AEC−Q100 2 IN A Qualified and PPAP Capable 3 GND • These Devices are Pb−Free and are RoHS Compliant 4 OUT Y 5 VCC NC 1 5 VCC
FUNCTION TABLE
IN A 2
A Input Y Output
GND 3 4 OUT Y L L H H
Figure 1. Pinout
(Top View) 1 IN A OUT Y
ORDERING INFORMATION Figure 2. Logic Symbol
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
October, 2015 − Rev. 16 MC74VHC1GT50/D
TTL−Compatible Inputs
The MC74VHC1GT50 is a single gate noninverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
www.onsemi.com
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.
MARKING
The device input is compatible with TTL−type input thresholds and
DIAGRAMS
the output has a full 5 V CMOS level output swing. The input protection 5 5 circuitry on this device allows overvoltage tolerance on the input, M allowing the device to be used as a logic−level translator from 3 V 1 VL M G G CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
SC−88A / SOT−353 / SC−70
CMOS Logic while operating at the high−voltage power supply.
DF SUFFIX
1 The MC74VHC1GT50 input structure provides protection when
CASE 419A
voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74VHC1GT50 to be used to interface high voltage to 5 low voltage circuits. The output structures also provide protection 5 VL M G when VCC = 0 V. These input and output structures help prevent G device destruction caused by supply voltage − input/output voltage 1 1 mismatch, battery backup, hot insertion, etc.
TSOP−5 / SOT−23 / SC−59 DT SUFFIX Features
•
CASE 483
Designed for 1.65 V to 5.5 VCC Operation • High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V VL = Device Code • Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C M = Date Code* • G = Pb−Free Package TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V, VCC = 5 V • (Note: Microdot may be in either location) CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load *Date Code orientation and/or position may vary • Power Down Protection Provided on Inputs and Outputs depending upon manufacturing location. • Balanced Propagation Delays • Pin and Function Compatible with Other Standard Logic Families • Chip Complexity: FETs = 104; Equivalent Gates = 26
PIN ASSIGNMENT
• NLV Prefix for Automotive and Other Applications Requiring 1 NC Unique Site and Control Change Requirements; AEC−Q100 2 IN A Qualified and PPAP Capable 3 GND • These Devices are Pb−Free and are RoHS Compliant 4 OUT Y 5 VCC NC 1 5 VCC
FUNCTION TABLE
IN A 2
A Input Y Output
GND 3 4 OUT Y L L H H
Figure 1. Pinout
(Top View) 1 IN A OUT Y
ORDERING INFORMATION Figure 2. Logic Symbol
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
October, 2015 − Rev. 16 MC74VHC1GT50/D