Datasheet LT8471 (Analog Devices) - 7

LT8471
pin FuncTions C1, C2 (Pins 1, 20):
Collector Pins. These are the collec- pulled low when their respective output voltages are more tors of the primary internal NPN power switches. If either than 7.5% below their target output voltages (as set by pin is tied to a DC voltage, it must be locally bypassed; if the external feedback resistors). When the output voltage either pin is a switching pin, minimize trace area connected is above 92.5% of the target voltage, the respective PG to the pin to minimize EMI. When the Skyhook channel is pin driver turns off, allowing the PG voltage to rise and used, the C2 pin must be tied to the input voltage of the indicate that the regulated output voltage is good. Skyhook channel.
RT (Pin 7):
Timing Resistor Pin. Adjusts the switching
C3 (Pin 13):
Skyhook Collector Pin. This is the collector of frequency. Place a resistor from this pin to ground to set the internal NPN power switch for the Skyhook channel. the frequency to a fixed free-running level. Do not float If the Skyhook channel is used, minimize the metal trace this pin. area connected to this pin to minimize EMI. If the Skyhook
SHOUT (Pin 14):
Skyhook Output Voltage Pin. This is the channel is not used, tie the C3 pin to GND. cathode of the internal Schottky diode and the output of
E1, E2 (Pins 2, 19):
Emitter Pins. These are the emit- the Skyhook boost converter. ters of the primary internal NPN power switches. Unless
SS1, SS2 (Pins 8, 15):
Soft Start Pins. Place a soft-start grounded, minimize trace area connected to these pins capacitor on each pin. Upon start-up, the SS pins will be to minimize EMI. charged by (nominally) 250k resistors to about 2.15V.
FB1, FB2 (Pins 5, 16):
Feedback Pins for Primary Chan-
SYNC (Pin 9):
To synchronize the switching frequency nels. Connect a resistor divider between VOUT, FB and to an outside clock, simply drive this pin with a clock. GND to set the output voltage. The high voltage level of the clock needs to exceed 1.3V,
GND (Pins 10, 11,12, Exposed Pad 21):
Ground. All of the and the low level should be less than 0.4V. Drive this pin ground pins must be soldered directly to the local ground to less than 0.4V to revert to the internal free running plane. The exposed pad metal of the package provides both clock. See the Applications Information section for more electrical contact to ground and good thermal contact to information. the printed circuit board.
VIN1 (Pin 3):
Input Supply Pin 1. This is the power supply
OV/UV (Pin 6)
: Overvoltage/Undervoltage Pin. Tie to 1.215V pin for primary channel 1 and the Skyhook channel. This (typical) or more to enable the device; ground to shut down. pin also provides power to additional circuitry common Configurable as a UVLO and OVLO by connecting to an to all channels. VIN1 must be greater than 2.6V for any external resistor divider. See the Applications Information channel to operate. VIN1 must be locally bypassed. section for more information.
VIN2 (Pin 18):
Input Supply Pin 2. This is the power supply
PG1, PG2 (Pins 4, 17):
Power Good Pins. Connect pull-up pin for primary channel 2 and must be greater than 2.6V resistors to these pins. These open-drain output pins are when channel 2 is in use. VIN2 must be locally bypassed. 8471fd For more information www.linear.com/8471 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Related Parts