Datasheet LTC1871-1 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | Wide Input Range, No RSENSE Current Mode Boost, Flyback and SEPIC Controller |
| 页数 / 页 | 36 / 7 — PIN FUNCTIONS. MODE/SYNC (Pin 5):. INTVCC (Pin 8):. IN (Pin 9):. SENSE … |
| 文件格式/大小 | PDF / 538 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS. MODE/SYNC (Pin 5):. INTVCC (Pin 8):. IN (Pin 9):. SENSE (Pin 10):. GND (Pin 6):. GATE (Pin 7):. BLOCK DIAGRAM
该数据表的模型线
文件文字版本
LTC1871-1
PIN FUNCTIONS MODE/SYNC (Pin 5):
This input controls the operating
INTVCC (Pin 8):
The Internal 5.20V Regulator Output. mode of the converter and allows for synchronizing the The gate driver and control circuits are powered from operating frequency to an external clock. If the MODE/ this voltage. Decouple this pin locally to the IC ground SYNC pin is connected to ground, Burst Mode operation with a minimum of 4.7μF low ESR tantalum or ceramic is enabled. If the MODE/SYNC pin is connected to INTVCC, capacitor. or if an external logic-level synchronization signal is ap-
V
plied to this input, Burst Mode operation is disabled and
IN (Pin 9):
Main Supply Pin. Must be closely decoupled to ground. the IC operates in a continuous mode.
SENSE (Pin 10):
The Current Sense Input for the Control
GND (Pin 6):
Ground Pin. Loop. Connect this pin to the drain of the power MOSFET
GATE (Pin 7):
Gate Driver Output. for VDS sensing and highest effi ciency. Alternatively, the SENSE pin may be connected to a resistor in the source of the power MOSFET. Internal leading edge blanking is provided for both sensing methods.
BLOCK DIAGRAM
RUN + 1 BIAS AND SLOPE START-UP C2 COMPENSATION CONTROL – 1.248V FREQ VIN 4 V-TO-I OSC 9 0.6V MODE/SYNC IOSC INTVCC 5 GATE PWM LATCH 50k LOGIC 7 85mV S + – OV 1.230V Q R GND + BURST CURRENT SENSE COMPARATOR COMPARATOR + 0.175V + 10 FB – EA C1 – 3 – gm + 1.230V ITH 2 V-TO-I INTV R CC I LOOP LOOP 5.2V 8 LDO 1.230V SLOPE 1.230V UV – TO GND START-UP BIAS VREF 6 + CONTROL 18711 BD 2.00V VIN 18711fb 7
PIN FUNCTIONS MODE/SYNC (Pin 5):
This input controls the operating
INTVCC (Pin 8):
The Internal 5.20V Regulator Output. mode of the converter and allows for synchronizing the The gate driver and control circuits are powered from operating frequency to an external clock. If the MODE/ this voltage. Decouple this pin locally to the IC ground SYNC pin is connected to ground, Burst Mode operation with a minimum of 4.7μF low ESR tantalum or ceramic is enabled. If the MODE/SYNC pin is connected to INTVCC, capacitor. or if an external logic-level synchronization signal is ap-
V
plied to this input, Burst Mode operation is disabled and
IN (Pin 9):
Main Supply Pin. Must be closely decoupled to ground. the IC operates in a continuous mode.
SENSE (Pin 10):
The Current Sense Input for the Control
GND (Pin 6):
Ground Pin. Loop. Connect this pin to the drain of the power MOSFET
GATE (Pin 7):
Gate Driver Output. for VDS sensing and highest effi ciency. Alternatively, the SENSE pin may be connected to a resistor in the source of the power MOSFET. Internal leading edge blanking is provided for both sensing methods.
BLOCK DIAGRAM
RUN + 1 BIAS AND SLOPE START-UP C2 COMPENSATION CONTROL – 1.248V FREQ VIN 4 V-TO-I OSC 9 0.6V MODE/SYNC IOSC INTVCC 5 GATE PWM LATCH 50k LOGIC 7 85mV S + – OV 1.230V Q R GND + BURST CURRENT SENSE COMPARATOR COMPARATOR + 0.175V + 10 FB – EA C1 – 3 – gm + 1.230V ITH 2 V-TO-I INTV R CC I LOOP LOOP 5.2V 8 LDO 1.230V SLOPE 1.230V UV – TO GND START-UP BIAS VREF 6 + CONTROL 18711 BD 2.00V VIN 18711fb 7