Datasheet LT1680 (Analog Devices) - 6

LT1680
W U TYPICAL PERFOR A CE CHARACTERISTICS RUN/SHDN Input Current Operating Frequency vs Pin Voltage Maximum Duty Cycle vs RCT (Normalized) vs Temperature
600 100 1.01 FULL OPERATING 90 TEMPERATURE IDISCHG = 2.75mA µA) RANGE 80 450 UPPER LIMIT 70 1.00 60 TYPICAL 300 50 I 40 DISCHG = 2.1mA LOWER 0.99 LIMIT 30 150 MAXIMUM DUTY CYCLE (%) 20 FULL OPERATING RUN/SHDN INPUT CURRENT ( TEMPERATURE 10 RANGE OPERATING FREQUENCY (NORMALIZED) 0 0 0.98 0 2 4 6 8 10 12 1 2 4 6 10 20 40 60 100 –50 –25 0 25 50 75 100 125 RUN/SHDN PIN VOLTAGE (V) RCT (kΩ) TEMPERATURE (°C) 1680 G20 1680 G19 1680 G21
U U U PI FU CTIO S SL/ADJ (Pin 1):
Slope Compensation Adjustment. Allows
SS (Pin 4):
Soft Start. Generates ramping threshold for increased slope compensation for certain high duty cycle regulator current limit during start-up and after UVLO applications. Resistive loading of this pin increases effec- events by sourcing about 8µA into an external capacitor. tive slope compensation. A resistor divider from the 5VREF
V
pin can tailor the onset of additional slope compensation
C (Pin 5):
Error Amplifier Output. RC load creates domi- nant compensation in power supply regulation feedback to specific regions in each switch cycle. Pin can be floated loop to provide optimum transient response. (See Appli- or connected to 5VREF if no additional slope compensation cations Information section for compensation details.) is required. (See Applications Information section for slope compensation details.)
SGND (Pin 6):
Small-Signal Ground. Connect to negative terminal of C
C
OUT.
T (Pin 2):
Oscillator Timing Pin. Connect a capacitor (C
V
CT) to ground and a pull-up resistor (RCT) to the 5VREF
FB (Pin 7):
Error Amplifier Inverting Input. Used as supply. Typical values are C voltage feedback input node for regulator loop. Pin sources CT = 1000pF and 10k ≤ RCT ≤ 30k. about 0.5µA DC bias current to protect from an open feedback path condition.
IAVG (Pin 3):
Average Current Limit Integration. The frequency response characteristic is set using 50kΩ
VREF (Pin 8):
Bandgap Generated Voltage Reference output impedance of this pin and external capacitor. The Decoupling. Connect a capacitor to signal ground. (Typi- external capacitor is typically connected from the I cal capacitor value ≈ 0.1µF.) AVG pin to the VC pin, but can also be connected from the IAVG pin
SENSE + (Pin 9):
Current Sense Amplifier Inverting Input. to ground. Connecting the capacitor from the IAVG pin to Connect to most positive (DC) terminal of current sense the VC pin uses an internal gain block to form an active resistor. integrator, minimizing the capacitance required for stable operation. A typical value for this integration capacitor is
SENSE – (Pin 10):
Current Sense Amplifier Noninverting 220pF from I Input. Connect to most negative (DC) terminal of current AVG to VC. Shorting this pin to SGND will disable the average current limit function. sense resistor. 6