Datasheet ATtiny28L, ATtiny28V (Atmel)

Features
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Utilizes the AVR® RISC Architecture
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AVR – High-performance and Low-power RISC Architecture – 90 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General-purpose Working Registers – Up to 4 MIPS Throughput at 4 MHz
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Nonvolatile Program Memory – 2K Bytes of Flash Program Memory – Endurance: 1,000 Write/Erase Cycles – Programming Lock for Flash Program Data Security
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Peripheral Features 8-bit – Interrupt and Wake-up on Low-level Input – One 8-bit Timer/Counter with Separate Prescaler Microcontroller – On-chip Analog Comparator – Programmable Watchdog Timer with On-chip Oscillator with 2K Bytes of – Built-in High-current LED Driver with Programmable Modulation
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Special Microcontroller Features – Low-power Idle and Power-down Modes Flash – External and Internal Interrupt Sources – Power-on Reset Circuit with Programmable Start-up Time – Internal Calibrated RC Oscillator
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Power Consumption at 1 MHz, 2V, 25
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C ATtiny28L – Active: 3.0 mA – Idle Mode: 1.2 mA ATtiny28V – Power-down Mode: <1 µA
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I/O and Packages – 11 Programmable I/O Lines, 8 Input Lines and a High-current LED Driver – 28-lead PDIP, 32-lead TQFP, and 32-pad MLF
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Operating Voltages – VCC: 1.8V - 5.5V for the ATtiny28V – V : 2.7V - 5.5V for the ATtiny28L CC
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Speed Grades – 0 - 1.2 MHz for the ATtiny28V – 0 - 4 MHz For the ATtiny28L Pin Configurations
PDIP TQFP/QFN/MLF RESET 1 28 PA0 PD2 PD1 PD0 RESET PA0 PA1 PA3 PA2 (IR) PD0 2 27 PA1 PD1 3 26 PA3 32 31 30 29 28 27 26 25 PD2 4 25 PA2 (IR) PD3 1 24 PB7 PD3 5 24 PB7 PD4 2 23 PB6 PD4 6 23 PB6 NC 3 22 NC VCC 7 22 GND VCC 4 21 GND GND 8 21 NC GND 5 20 NC XTAL1 9 20 VCC NC 6 19 NC XTAL1 7 18 VCC XTAL2 10 19 PB5 XTAL2 8 17 PB5 PD5 11 18 PB4 (INT1) PD6 12 17 PB3 (INT0) 9 10 11 12 13 14 15 16 PD7 13 16 PB2 (T0) (AIN0) PB0 14 15 PB1 (AIN1) PD5 PD6 PD7 (T0) PB2 (AIN0) PB0 (AIN1) PB1 (INT0) PB3 (INT1) PB4 Rev. 1062F–AVR–07/06
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Document Outline Features Pin Configurations Description Block Diagram Pin Descriptions VCC GND Port A (PA3..PA0) Port B (PB7..PB0) Port D (PD7..PD0) XTAL1 XTAL2 RESET Architectural Overview ALU - Arithmetic Logic Unit Subroutine and Interrupt Hardware Stack General-purpose Register File Status Register Status Register - SREG System Clock and Clock Options Internal RC Oscillator Calibrated Internal RC Oscillator Crystal Oscillator External Clock External RC Oscillator Register Description Oscillator Calibration Register - OSCCAL Memories I/O Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Indirect Register Direct, Two Registers Rd and Rr I/O Direct Relative Program Addressing, RJMP and RCALL Constant Addressing Using the LPM Instruction Memory Access and Instruction Execution Timing Flash Program Memory Sleep Modes Idle Mode Power-down Mode System Control and Reset Reset Sources Power-on Reset External Reset Watchdog Reset Register Description MCU Control and Status Register - MCUCS Interrupts Reset and Interrupt Interrupt Handling Interrupt Response Time External Interrupt Low-level Input Interrupt Register Description Interrupt Control Register - ICR Interrupt Flag Register - IFR I/O Ports Port A Port A as General Digital I/O Alternate Function of PA2 Port A Schematics Port B Port B as General Digital Input Alternate Functions of Port B Port B Schematics Port D Port D as General Digital I/O Register Description Port A Data Register - PORTA Port A Control Register - PACR Port A Input Pins Address - PINA Port B Input Pins Address - PINB Port D Data Register - PORTD Port D Data Direction Register - DDRD Port D Input Pins Address - PIND Timer/Counter0 Timer/Counter Prescaler Register Description Timer/Counter0 Control Register - TCCR0 Timer Counter 0 - TCNT0 Watchdog Timer Register Description Watchdog Timer Control Register - WDTCR Hardware Modulator Register Description Modulation Control Register - MODCR Analog Comparator Register Description Analog Comparator Control and Status Register - ACSR Memory Programming Program Memory Lock Bits Fuse Bits Signature Bytes Calibration Byte Programming the Flash Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Reading the Flash Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes and Calibration Byte Parallel Programming Characteristics Electrical Characteristics Absolute Maximum Ratings DC Characteristics External Clock Drive Waveforms External Clock Drive Typical Characteristics Register Summary Instruction Set Summary Ordering Information Packaging Information 32A 28P3 32M1-A Errata All revisions Datasheet Revision History Rev - 01/06G Rev - 01/06G Rev - 03/05F Table of Contents