Datasheet ATtiny28L, ATtiny28V (Atmel) - 5

ATtiny28L/V
r a t e i n t e r r u p t v e c t o r i n t h e i n t e r r u p t v e c t o r t a b l e a t t h e b e g i n n i n g o f t h e program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority.
ALU – Arithmetic Logic
The high-performance AVR ALU operates in direct connection with all the 32 general-
Unit
purpose working registers. Within a single clock cycle, ALU operations between regis- ters in the register file are executed. The ALU operations are divided into three main categories – arithmetic, logic and bit functions. Some microcontrollers in the AVR prod- uct family feature a hardware multiplier in the arithmetic part of the ALU.
Subroutine and Interrupt
The ATtiny28 uses a 3-level-deep hardware stack for subroutines and interrupts. The
Hardware Stack
hardware stack is 10 bits wide and stores the program counter (PC) return address while subroutines and interrupts are executed. RCALL instructions and interrupts push the PC return address onto stack level 0, and the data in the other stack levels 1 - 2 are pushed one level deeper in the stack. When a RET or RETI instruction is executed the returning PC is fetched from stack level 0, and the data in the other stack levels 1 - 2 are popped one level in the stack. If more than three subsequent subroutine calls or interrupts are executed, the first val- ues written to the stack are overwritten.
General-purpose
Figure 4 shows the structure of the 32 general-purpose registers in the CPU.
Register File Figure 4.
AVR CPU General-purpose Working Registers 7 0 R0 R1 R2 General … Purpose … Working R28 Registers R29 R30 (Z-Register low byte) R31(Z-Register high byte) All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only exception are the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the register file – R16..R31. The general SBC, SUB, CP, AND, OR and all other operations between two registers or on a single register apply to the entire register file. Registers 30 and 31 form a 16-bit pointer (the Z-pointer), which is used for indirect Flash memory and register file access. When the register file is accessed, the contents of R31 are discarded by the CPU.
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1062F–AVR–07/06 Document Outline Features Pin Configurations Description Block Diagram Pin Descriptions VCC GND Port A (PA3..PA0) Port B (PB7..PB0) Port D (PD7..PD0) XTAL1 XTAL2 RESET Architectural Overview ALU - Arithmetic Logic Unit Subroutine and Interrupt Hardware Stack General-purpose Register File Status Register Status Register - SREG System Clock and Clock Options Internal RC Oscillator Calibrated Internal RC Oscillator Crystal Oscillator External Clock External RC Oscillator Register Description Oscillator Calibration Register - OSCCAL Memories I/O Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Indirect Register Direct, Two Registers Rd and Rr I/O Direct Relative Program Addressing, RJMP and RCALL Constant Addressing Using the LPM Instruction Memory Access and Instruction Execution Timing Flash Program Memory Sleep Modes Idle Mode Power-down Mode System Control and Reset Reset Sources Power-on Reset External Reset Watchdog Reset Register Description MCU Control and Status Register - MCUCS Interrupts Reset and Interrupt Interrupt Handling Interrupt Response Time External Interrupt Low-level Input Interrupt Register Description Interrupt Control Register - ICR Interrupt Flag Register - IFR I/O Ports Port A Port A as General Digital I/O Alternate Function of PA2 Port A Schematics Port B Port B as General Digital Input Alternate Functions of Port B Port B Schematics Port D Port D as General Digital I/O Register Description Port A Data Register - PORTA Port A Control Register - PACR Port A Input Pins Address - PINA Port B Input Pins Address - PINB Port D Data Register - PORTD Port D Data Direction Register - DDRD Port D Input Pins Address - PIND Timer/Counter0 Timer/Counter Prescaler Register Description Timer/Counter0 Control Register - TCCR0 Timer Counter 0 - TCNT0 Watchdog Timer Register Description Watchdog Timer Control Register - WDTCR Hardware Modulator Register Description Modulation Control Register - MODCR Analog Comparator Register Description Analog Comparator Control and Status Register - ACSR Memory Programming Program Memory Lock Bits Fuse Bits Signature Bytes Calibration Byte Programming the Flash Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Reading the Flash Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes and Calibration Byte Parallel Programming Characteristics Electrical Characteristics Absolute Maximum Ratings DC Characteristics External Clock Drive Waveforms External Clock Drive Typical Characteristics Register Summary Instruction Set Summary Ordering Information Packaging Information 32A 28P3 32M1-A Errata All revisions Datasheet Revision History Rev - 01/06G Rev - 01/06G Rev - 03/05F Table of Contents