Datasheet ATtiny28L, ATtiny28V (Atmel) - 9

ATtiny28L/V Register Description Oscillator Calibration Register – OSCCAL
Bit 7 6 5 4 3 2 1 0 $00
CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0
• Bits 7..0 – CAL7..CAL0: Oscillator Calibration Value
Writing the calibration byte to this address will trim the internal oscillator to remove pro- cess variation from the oscillator frequency. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to the register will increase the frequency to the internal oscillator. Writing $FF to the register gives the highest available fre- quency. Table 2 shows the range for OSCCAL. Note that the oscillator is intended for calibration to 1.2 MHz, thus tuning to other values is not guaranteed. At 3V and 25oC, the pre-programmed calibration byte gives a frequency within ± 1% of the nominal frequency.
Table 2.
Internal RC Oscillator Range
OSCCAL Value Min Frequency Max Frequency
0x00 0.6 MHz 1.2 MHz 0x7F 0.8 MHz 1.7 MHz 0xFF 1.2 MHz 2.5 MHz
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1062F–AVR–07/06 Document Outline Features Pin Configurations Description Block Diagram Pin Descriptions VCC GND Port A (PA3..PA0) Port B (PB7..PB0) Port D (PD7..PD0) XTAL1 XTAL2 RESET Architectural Overview ALU - Arithmetic Logic Unit Subroutine and Interrupt Hardware Stack General-purpose Register File Status Register Status Register - SREG System Clock and Clock Options Internal RC Oscillator Calibrated Internal RC Oscillator Crystal Oscillator External Clock External RC Oscillator Register Description Oscillator Calibration Register - OSCCAL Memories I/O Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Indirect Register Direct, Two Registers Rd and Rr I/O Direct Relative Program Addressing, RJMP and RCALL Constant Addressing Using the LPM Instruction Memory Access and Instruction Execution Timing Flash Program Memory Sleep Modes Idle Mode Power-down Mode System Control and Reset Reset Sources Power-on Reset External Reset Watchdog Reset Register Description MCU Control and Status Register - MCUCS Interrupts Reset and Interrupt Interrupt Handling Interrupt Response Time External Interrupt Low-level Input Interrupt Register Description Interrupt Control Register - ICR Interrupt Flag Register - IFR I/O Ports Port A Port A as General Digital I/O Alternate Function of PA2 Port A Schematics Port B Port B as General Digital Input Alternate Functions of Port B Port B Schematics Port D Port D as General Digital I/O Register Description Port A Data Register - PORTA Port A Control Register - PACR Port A Input Pins Address - PINA Port B Input Pins Address - PINB Port D Data Register - PORTD Port D Data Direction Register - DDRD Port D Input Pins Address - PIND Timer/Counter0 Timer/Counter Prescaler Register Description Timer/Counter0 Control Register - TCCR0 Timer Counter 0 - TCNT0 Watchdog Timer Register Description Watchdog Timer Control Register - WDTCR Hardware Modulator Register Description Modulation Control Register - MODCR Analog Comparator Register Description Analog Comparator Control and Status Register - ACSR Memory Programming Program Memory Lock Bits Fuse Bits Signature Bytes Calibration Byte Programming the Flash Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Reading the Flash Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes and Calibration Byte Parallel Programming Characteristics Electrical Characteristics Absolute Maximum Ratings DC Characteristics External Clock Drive Waveforms External Clock Drive Typical Characteristics Register Summary Instruction Set Summary Ordering Information Packaging Information 32A 28P3 32M1-A Errata All revisions Datasheet Revision History Rev - 01/06G Rev - 01/06G Rev - 03/05F Table of Contents