Datasheet ATtiny11, ATtiny12 - Summary (Atmel) - 2
| 制造商 | Atmel |
| 描述 | 8-bit AVR Microcontroller with 1K Byte Flash |
| 页数 / 页 | 15 / 2 — Overview. Table 1. Device. Flash. EEPROM. Register. Voltage Range. … |
| 文件格式/大小 | PDF / 235 Kb |
| 文件语言 | 英语 |
Overview. Table 1. Device. Flash. EEPROM. Register. Voltage Range. Frequency. ATtiny11/12
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文件文字版本
Overview
The ATtiny11/12 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny11/12 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general-purpose working regis- ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
Table 1.
Parts Description
Device Flash EEPROM Register Voltage Range Frequency
ATtiny11L 1K - 32 2.7 - 5.5V 0-2 MHz ATtiny11 1K - 32 4.0 - 5.5V 0-6 MHz ATtiny12V 1K 64 B 32 1.8 - 5.5V 0-1.2 MHz ATtiny12L 1K 64 B 32 2.7 - 5.5V 0-4 MHz ATtiny12 1K 64 B 32 4.0 - 5.5V 0-8 MHz The ATtiny11/12 AVR is supported with a full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
2 ATtiny11/12
1006FS–AVR–06/07 Document Outline Features Pin Configuration Overview ATtiny11 Block Diagram ATtiny12 Block Diagram Pin Descriptions VCC GND Port B (PB5..PB0) XTAL1 XTAL2 RESET Register Summary ATtiny11 Register Summary ATtiny12 Instruction Set Summary Ordering Information ATtiny11 ATtiny12 Packaging Information 8P3 8S2 Datasheet Revision History Rev. 1006F-06/07 Rev. 1006E-07/06 Rev. 1006D-07/03 Rev. 1006C-09/01
The ATtiny11/12 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny11/12 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general-purpose working regis- ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
Table 1.
Parts Description
Device Flash EEPROM Register Voltage Range Frequency
ATtiny11L 1K - 32 2.7 - 5.5V 0-2 MHz ATtiny11 1K - 32 4.0 - 5.5V 0-6 MHz ATtiny12V 1K 64 B 32 1.8 - 5.5V 0-1.2 MHz ATtiny12L 1K 64 B 32 2.7 - 5.5V 0-4 MHz ATtiny12 1K 64 B 32 4.0 - 5.5V 0-8 MHz The ATtiny11/12 AVR is supported with a full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
2 ATtiny11/12
1006FS–AVR–06/07 Document Outline Features Pin Configuration Overview ATtiny11 Block Diagram ATtiny12 Block Diagram Pin Descriptions VCC GND Port B (PB5..PB0) XTAL1 XTAL2 RESET Register Summary ATtiny11 Register Summary ATtiny12 Instruction Set Summary Ordering Information ATtiny11 ATtiny12 Packaging Information 8P3 8S2 Datasheet Revision History Rev. 1006F-06/07 Rev. 1006E-07/06 Rev. 1006D-07/03 Rev. 1006C-09/01