Datasheet ADE7854, ADE7858, ADE7868, ADE7878 (Analog Devices) - 3

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Data Sheet ADE7854/ADE7858/ADE7868/ADE7878 REVISION HISTORY 4/14—Rev. G to Rev. H
Changes to Equation 20 and to Equation 21 ... 45 Changes to Power-Up Procedure Section .. 26 Changes to Active Energy Calculation Section ... 46 Changes to Crystal Circuit Section ... 76 Changes to Figure 62 and to fol owing text and to Equation 25 .. 47 Changes to Equation 32, Equation 34, and to Reactive
10/13—Rev. F to Rev. G
Power Gain Calibration Section .. 50 Changes to Product Title and Features Section .. 1 Changes to Reactive Energy Calculation Section ... 51 Changes to Table 2 .. 9 Changes to Figure 66 .. 52 Deleted Junction Temperature; Table 6 .. 15 Changes to Energy Accumulation Modes Sections and to Changes to NC and CLKIN Pin Descriptions ... 16 Caption for Figure 67 .. 53 Replaced Typical Performance Characteristics Section ... 18 Changes to Equation 40 ... 54 Added Text to Test Circuit Section ... 21 Changes to Apparent Power Calculation Using VNOM Section ... 55 Changes to Terminology Section .. 22 Changes to CF Outputs for Various Accumultation Modes Changes to PSM2—Low Power Mode (ADE7868, ADE7878 Section .. 60 Only) Section and Added Figure 25 ... 24 Changes to Sign of Sum-of-Phase Powers in the CFx Changes to Changing Phase Voltage Datapath Section and Datapath Section and to Equation 47 ... 61 Figure 42 ... 33 Changes to Equation 48 ... 62 Changes to Reference Circuit Section; Added Figure 56, Changes to Checksum Register Section and to Table 23 ... 63 Figure 57, and Figure 58; Renumbered Sequentially .. 41 Changes to Figure 81 .. 66 Changes to Current RMS Compensation Section ... 44 Changes to Figure 82 .. 67 Changes to Current Mean Absolute Value Calculation— Changes to SPI-Compatible Interface Section .. 68 ADE7868 and ADE7878 Only and Figure 60 .. 45 Changes to HSDC Interface Section .. 70 Changes to Voltage RMS Offset Compensation Section ... 47 Changes to Figure 88 .. 71 Changes to Line Cycle Active Energy Accumulation Mode Changes to Figure 89, added Quick Setup as Energy Meter Section ... 51 Section, added Layout Guidelines, and added Figure 90; Changes to Quick Setup as Energy Meter Section and Renumbered Sequentially .. 72 Figure 95 ... 75 Added Figure 91 and Figure 92 ... 73 Changes to Figure 96 and Figure 97; Added Crystal Circuit Changes to Table 30 .. 78 Section .. 76 Changes to Table 33 .. 79 Changes to Address 0xE520 Description; Table 33 .. 84 Changes to Table 46 .. 90 Changes to Bit 11, Bit 12, Bit 13 Descriptions; Table 43 .. 91
4/11—Rev. D to Rev. E
Updated Outline Dimensions .. 99 Changes to Input Clock FrequencyParameter, Table 2 .. 10
10/12—Rev. E to Rev. F
Changes to Current RMS Offset Compensation Section .. 42 Changes to Figure 1 ... 4 Changes to Voltage RMS Offset Compensation Section ... 44 Changes to Figure 2 ... 5 Changes to Note 2, Table 30... 77 Changes to Figure 3 ... 6 Changes to Address 0xE707, Table 33 .. 80 Changes to Figure 4 ... 7 Changes to Table 45 .. 87 Changes to Table 2 .. 8 Changes to Table 46 .. 88 Changes to Figure 5 ... 11 Changes to Bit Location 7:3, Default Value, Table 54 .. 92 Added Text under Table 6 .. 14
2/11—Rev. C to Rev. D
Changes to Figure 9 and to Table 8 ... 15 Changes to Power-Up Procedure Section .. 24 Changes to Figure 1 .. 4 Changes to Figure 31 and Figure 32 ... 28 Changes to Figure 2 .. 5 Changes to Figure 39 .. 30 Changes to Figure 3 .. 6 Changes to Voltage Waveform Gain Register Section .. 31 Changes to Figure 4 .. 7 Changes to Figure 41 .. 32 Changes to Table 2 .. 8 Changes to Phase Compensation Section .. 37 Changed SCLK Edge to HSCLK Edge, Table 5 ... 13 Changes to Digital Signal Processor Section ... 39 Change to Current Channel HPF Section ... 28 Changes to Equation 12 .. 40 Change to di/dt Current Sensor and Digital Integrator Section .. 30 Changes to Current RMS Offset Compensation Section .. 42 Changes to Digital Signal Processor Section ... 39 Changes to Voltage Channel RMS Calculation Section ... 43 Changes to Figure 59 .. 44 Changes to Voltage RMS Offset Compensation Section and Changes to Figure 62 .. 47 to Figure 59 .. 44 Changes to Figure 65 .. 49 Changes to Figure 66 .. 52 Rev. H | Page 3 of 100 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagrams Specifications Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuit Terminology Power Management PSM0—Normal Power Mode (All Parts) PSM1—Reduced Power Mode (ADE7868, ADE7878 Only) PSM2—Low Power Mode (ADE7868, ADE7878 Only) PSM3—Sleep Mode (All Parts) Power-Up Procedure Hardcore Reset Software Reset Functionality Theory of Operation Analog Inputs Analog-to-Digital Conversion Antialiasing Filter ADC Transfer Function Current Channel ADC Current Waveform Gain Registers Current Channel HPF Current Channel Sampling di/dt Current Sensor and Digital Integrator Voltage Channel ADC Voltage Waveform Gain Registers Voltage Channel HPF Voltage Channel Sampling Changing Phase Voltage Datapath POWER QUALITY MEASUREMENTS Zero-Crossing Detection Zero-Crossing Timeout Phase Sequence Detection Time Interval Between Phases Period Measurement Phase Voltage Sag Detection SAG Level Set Peak Detection Overvoltage and Overcurrent Detection Overvoltage and Overcurrent Level Set Neutral Current Mismatch—ADE7868, ADE7878 Phase Compensation Reference Circuit Digital Signal Processor Root Mean Square Measurement Current RMS Calculation Current RMS Offset Compensation Current Mean Absolute Value Calculation—ADE7868 and ADE7878 Only Current MAV Gain and Offset Compensation Voltage Channel RMS Calculation Voltage RMS Offset Compensation Active Power Calculation Total Active Power Calculation Fundamental Active Power Calculation—ADE7878 Only Active Power Gain Calibration Active Power Offset Calibration Sign of Active Power Calculation Active Energy Calculation Integration Time Under Steady Load Energy Accumulation Modes Line Cycle Active Energy Accumulation Mode Reactive Power Calculation—ADE7858, ADE7868, ADE7878 Only Reactive Power Gain Calibration Reactive Power Offset Calibration Sign of Reactive Power Calculation Reactive Energy Calculation Integration Time Under A Steady Load Energy Accumulation Modes Line Cycle Reactive Energy Accumulation Mode Apparent Power Calculation Apparent Power Gain Calibration Apparent Power Offset Calibration Apparent Power Calculation Using VNOM Apparent Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode Line Cycle Apparent Energy Accumulation Mode Waveform Sampling Mode Energy-to-Frequency Conversion Synchronizing Energy Registers with CFx Outputs CF Outputs for Various Accumulation Modes Sign of Sum-of-Phase Powers in the CFx Datapath No Load Condition No Load Detection Based On Total Active, Reactive Powers No Load Detection Based on Fundamental Active and Reactive Powers—ADE7878 Only No Load Detection Based on Apparent Power Checksum Register Interrupts Using the Interrupts with an MCU Serial Interfaces Serial Interface Choice I2C-Compatible Interface I2C Write Operation I2C Read Operation SPI-Compatible Interface SPI Read Operation SPI Write Operation HSDC Interface Quick Setup as Energy Meter Layout Guidelines Crystal Circuit ADE7878 Evaluation Board Die Version Silicon Anomaly ADE7854/ADE7858/ADE7868/ADE7878 Functionality Issues Functionality Issues SECTION 1. ADE7854/ADE7858/ADE7868/ADE7878 Functionality Issues Registers List Outline Dimensions Ordering Guide