Datasheet ADE7763 (Analog Devices) - 9

link to page 14 link to page 29 link to page 16 link to page 18 link to page 10
Data Sheet ADE7763 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RESET 1 20 DIN DVDD 2 19 DOUT AVDD 3 18 SCLK V1P 4 17 CS ADE7763 V1N 5 16 CLKOUT TOP VIEW V2N 6 15 CLKIN (Not to Scale) V2P 7 14 IRQ AGND 8 13 SAG REFIN/OUT 9 12 ZX DGND 10 11 CF
04481-A-005 Figure 5. Pin Configuration (SSOP Package)
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 RESET Reset Pin1. A logic low on this pin holds the ADCs and digital circuitry (including the serial interface) in a reset condition. 2 DVDD Digital Power Supply. This pin provides the supply voltage for the digital circuitry. The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled to DGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor. 3 AVDD Analog Power Supply. This pin provides the supply voltage for the analog circuitry. The supply should be maintained at 5 V ± 5% for specified operation. Minimize power supply ripple and noise at this pin by using proper decoupling. The typical performance graphs show the power supply rejection performance. This pin should be decoupled to AGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor. 4, 5 V1P, V1N Analog Inputs for Channel 1. This channel is intended for use with a di/dt current transducer, i.e., a Rogowski coil or another current sensor such as a shunt or current transformer (CT). These inputs are fully differential voltage inputs with maximum differential input signal levels of ±0.5 V, ±0.25 V, and ±0.125 V, depending on the full-scale selection—see the Analog Inputs section. Channel 1 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is ±0.5 V. Both inputs have internal ESD protection circuitry and can sustain an overvoltage of ±6 V without risk of permanent damage. 6, 7 V2N, V2P Analog Inputs for Channel 2. This channel is intended for use with the voltage transducer. These inputs are fully differential voltage inputs with a maximum differential signal level of ±0.5 V. Channel 2 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is ±0.5 V. Both inputs have internal ESD protection circuitry and can sustain an overvoltage of ±6 V without risk of permanent damage. 8 AGND Analog Ground Reference. This pin provides the ground reference for the analog circuitry, i.e., ADCs and reference. This pin should be tied to the analog ground plane or to the quietest ground reference in the system. Use this quiet ground reference for all analog circuitry, such as antialiasing filters and current and voltage transducers. To minimize ground noise around the ADE7763, connect the quiet ground plane to the digital ground plane at only one point. It is acceptable to place the entire device on the analog ground plane. 9 REFIN/OUT Access to the On-Chip Voltage Reference. The on-chip reference has a nominal value of 2.4 V ± 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source can also be connected at this pin. In either case, this pin should be decoupled to AGND with a 10 µF capacitor in parallel with a 100nF ceramic capacitor. 10 DGND Digital Ground Reference. This pin provides the ground reference for the digital circuitry, i.e., multiplier, filters, and digital-to-frequency converter. Because the digital return currents in the ADE7763 are small, it is acceptable to connect this pin to the analog ground plane of the system. However, high bus capacitance on the DOUT pin could result in noisy digital current, which could affect performance. 11 CF Calibration Frequency Logic Output. The CF logic output gives active power information. This output is intended to be used for operational and calibration purposes. The full-scale output frequency can be adjusted by writing to the CFDEN and CFNUM registers—see the Energy-to-Frequency Conversion section. 12 ZX Voltage Waveform (Channel 2) Zero-Crossing Output. This output toggles logic high and logic low at the zero crossing of the differential signal on Channel 2—see the Zero-Crossing Detection section. 13 SAG This open-drain logic output goes active low when either no zero crossings are detected or a low voltage threshold (Channel 2) is crossed for a specified duration—see the Line Voltage Sag Detection section. Rev. C | Page 9 of 56 Document Outline Features General Description Functional Block Diagram Revision History Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Terminology Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Analog Inputs di/dt Current Sensor and Digital Integrator Zero-Crossing Detection Zero-Crossing Timeout Period Measurement Power Supply Monitor Line Voltage Sag Detection Sag Level Set Peak Detection Peak Level Set Peak Level Record Interrupts Using Interrupts with an MCU Interrupt Timing Temperature Measurement Analog-to-Digital Conversion Antialias Filter ADC Transfer Function Reference Circuit Channel 1 ADC Channel 1 Sampling Channel 1 RMS Calculation Channel 1 RMS Offset Compensation Channel 2 ADC Channel 2 Sampling Channel 2 RMS Calculation Channel 2 RMS Offset Compensation Phase Compensation Active Power Calculation Energy Calculation Integration Time under Steady Load Power Offset Calibration Energy-to-Frequency Conversion Line Cycle Energy Accumulation Mode Positive-Only Accumulation Mode No-Load Threshold Apparent Power Calculation Apparent Power Offset Calibration Apparent Energy Calculation Integration Times under Steady Load Line Apparent Energy Accumulation Energies Scaling Calibrating an Energy Meter Watt Gain Calibrating Watt Gain Using a Reference Meter Example Calibrating Watt Gain Using an Accurate Source Example Watt Offset Calibrating Watt Offset Using a Reference Meter Example Calibrating Watt Offset with an Accurate Source Example Phase Calibration Calibrating Phase Using a Reference Meter Example Calibrating Phase with an Accurate Source Example VRMS and IRMS Calibration Apparent Energy CLKIN Frequency Suspending Functionality Checksum Register Serial Interface ADE7763 Serial Write Operation Serial Read Operation Registers Register Descriptions Communication Register Mode Register (0x09) Outline Dimensions Ordering Guide CH1OS Register (0x0D) Outline Dimensions Ordering Guide