Datasheet LTC1052, LTC7652 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | Zero-Drift Operational Amplifier |
| 页数 / 页 | 24 / 6 — TYPICAL PERFOR A CE CHARACTERISTICS. Response Time vs Overdrive. TEST … |
| 文件格式/大小 | PDF / 871 Kb |
| 文件语言 | 英语 |
TYPICAL PERFOR A CE CHARACTERISTICS. Response Time vs Overdrive. TEST CIRCUITS. Electrical Characteristics Test Circuit (TC1)
该数据表的模型线
文件文字版本
LTC1052/LTC7652
W U TYPICAL PERFOR A CE CHARACTERISTICS Response Time vs Overdrive
VREF + OVERDRIVE INPUT { VREF – 1mV 10µV 5V 50µV OUTPUT 5µV {–5V 20ms/DIV
TEST CIRCUITS Electrical Characteristics Test Circuit (TC1) DC to 10Hz and DC to 1HZ Noise Test Circuit (TC3)
C2 C3 R2 1M R1 R2 R4 V+ 3 1k + 2 7 – V+ 6 OUTPUT C4 LT1001 6 2 7 R3 (NOISE x 20,000) LTC1052 OUTPUT – 2 – 3 8 + 6 4 R LTC1052 L R1 3 34k 1 8 + 4 0.1µF 0.1µF 1 34k 0.1µF 0.1µF V– LTC1052/7652 • TC01 V–
BANDWIDTH R1 R2 R3 R4 C2 C3 C4
10Hz 16.2Ω 162k 16.2k 16.2k 0.1µF 1.0µF 1.0µF 1Hz 16.2Ω 162k 162k 162k 1.0µF 1.0µF 1.0µF LTC1052/7652 • TC02
U THEORY OF OPERATIO DC OPERATION
The shaded portion of the LTC1052 block diagram stage. CEXTB and S2 act as a sample-and-hold to store the (Figure 1a) entirely determines the amplifier’s DC amplified input signal during the auto zero cycle. characteristics. During the auto zero portion of the cycle, By switching between these two states at a frequency the gm1 inputs are shorted together and a feedback path is much higher than the signal frequency, a continuous closed around the input stage to null its offset. Switch S2 output results. and capacitor CEXTA act as a sample-and-hold to store the Notice that during the auto zero cycle the g nulling voltage during the next step—the sampling cycle. m1 inputs are not only shorted together, but are also shorted to the In the sampling cycle, the zeroed amplifier is used to inverting input. This forces nulling with the common mode amplify the differential input voltage. Switch S2 connects voltage present and accounts for the extremely high the amplified input voltage to CEXTB and the output gain CMRR of the LTC1052. In the same fashion, variations in 1052fa 6
W U TYPICAL PERFOR A CE CHARACTERISTICS Response Time vs Overdrive
VREF + OVERDRIVE INPUT { VREF – 1mV 10µV 5V 50µV OUTPUT 5µV {–5V 20ms/DIV
TEST CIRCUITS Electrical Characteristics Test Circuit (TC1) DC to 10Hz and DC to 1HZ Noise Test Circuit (TC3)
C2 C3 R2 1M R1 R2 R4 V+ 3 1k + 2 7 – V+ 6 OUTPUT C4 LT1001 6 2 7 R3 (NOISE x 20,000) LTC1052 OUTPUT – 2 – 3 8 + 6 4 R LTC1052 L R1 3 34k 1 8 + 4 0.1µF 0.1µF 1 34k 0.1µF 0.1µF V– LTC1052/7652 • TC01 V–
BANDWIDTH R1 R2 R3 R4 C2 C3 C4
10Hz 16.2Ω 162k 16.2k 16.2k 0.1µF 1.0µF 1.0µF 1Hz 16.2Ω 162k 162k 162k 1.0µF 1.0µF 1.0µF LTC1052/7652 • TC02
U THEORY OF OPERATIO DC OPERATION
The shaded portion of the LTC1052 block diagram stage. CEXTB and S2 act as a sample-and-hold to store the (Figure 1a) entirely determines the amplifier’s DC amplified input signal during the auto zero cycle. characteristics. During the auto zero portion of the cycle, By switching between these two states at a frequency the gm1 inputs are shorted together and a feedback path is much higher than the signal frequency, a continuous closed around the input stage to null its offset. Switch S2 output results. and capacitor CEXTA act as a sample-and-hold to store the Notice that during the auto zero cycle the g nulling voltage during the next step—the sampling cycle. m1 inputs are not only shorted together, but are also shorted to the In the sampling cycle, the zeroed amplifier is used to inverting input. This forces nulling with the common mode amplify the differential input voltage. Switch S2 connects voltage present and accounts for the extremely high the amplified input voltage to CEXTB and the output gain CMRR of the LTC1052. In the same fashion, variations in 1052fa 6