AD8351Data Sheet400003500) 3000–25(ΩUDE T 2500NIrees)AGeg2000–50DM( E S1500A H3GHz10MHz10MHzDANCEPE P 1000–75IM500MHz500MHz3GHzWITH 50Ω500TERMINATIONS0–100WITHOUT 1 101001000TERMINATIONS -02 FREQUENCY (MHz) 145 03 24 0 45- 031 Figure 22. Input Impedance vs. Frequency Figure 25. Input Reflection Coefficient vs. Frequency (RS = RL = 100 Ω With and Without 50 Ω Terminations) 1603015025) (Ωrees)14020UDEegT(DNIEAG13015HASMP500MHz12010DANCE EDANCEPE P10MHzIMIM110510003GHz 2 101001000 -02 FREQUENCY (MHz) 145 03 025 45- 031 Figure 23. Output Impedance vs. Frequency Figure 26. Output Reflection Coefficient vs. Frequency (RS = RL = 100 Ω) 020 19–218 17–416 15)–614s)13(preesY–812Aeg11LDE(10ED–109PHAS8OUP–127GR6–145 4–163 1–1800255075100125150175200225250 023 5- FREQUENCY (MHz) 0314 Figure 24. Phase and Group Delay (AV = 10 dB, at 5 V Supplies) Rev. D | Page 10 of 19 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC CONCEPTS GAIN ADJUSTMENT COMMON-MODE ADJUSTMENT INPUT AND OUTPUT MATCHING SINGLE-ENDED-TO-DIFFERENTIAL OPERATION ADC DRIVING ANALOG MULTIPLEXING I/O CAPACITIVE LOADING TRANSMISSION LINE EFFECTS CHARACTERIZATION SETUP EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE