Datasheet AD8369 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 600 MHz, 45 dB Digitally Controlled Variable Gain Amplifier |
| 页数 / 页 | 24 / 4 — AD8369. SPECIFICATIONS (Continued). Parameter. Conditions. Min. Typ. Max. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 671 Kb |
| 文件语言 | 英语 |
AD8369. SPECIFICATIONS (Continued). Parameter. Conditions. Min. Typ. Max. Unit
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AD8369 SPECIFICATIONS (Continued) Parameter Conditions Min Typ Max Unit
Frequency = 380 MHz Voltage Gain 38.5 dB Gain Flatness Within ± 20 MHz of 380 MHz ±0.15 dB Noise Figure 7.8 dB Output IP3 f1 = 379.55 MHz, f2 = 380.45 MHz +8.5 dBV rms +8.5 dBm IMD3 f1 = 379.55 MHz, f2 = 380.45 MHz, VOPHI – VOPLO = 1 V p-p composite –47 dBc Harmonic Distortion Second-Order, VOPHI – VOPLO = 1 V p-p –45 dBc Third-Order, VOPHI – VOPLO = 1 V p-p –49 dBc P1dB For ± 1 dB deviation from linear gain +0.5 dBV rms +0.5 dBm Specifications subject to change without notice.
TIMING SPECIFICATIONS SERIAL PROGRAMMING TIMING REQUIREMENTS (VS = 5 V, T = 25
r
C) Parameter Typ Unit
Minimum Clock Pulsewidth (TPW) 10 ns Minimum Clock Period (TCK) 20 ns Minimum Setup Time Data vs. Clock (TDS) 2 ns Minimum Setup Time Data Enable vs. Clock (TES) 2 ns Minimum Hold Time Clock vs. Data Enable (TEH) 2 ns Minimum Hold Time Data vs. Clock (TDH) 4 ns
PARALLEL PROGRAMMING TIMING REQUIREMENTS (VS = 5 V, T = 25
r
C) Parameter Typ Unit
Minimum Setup Time Data Enable vs. Data (TES) 2 ns Minimum Hold Time Data Enable vs. Data (TEH) 2 ns
MSB
Minimum Data Enable Width (TPW) 4 ns
(BIT3) MSB–1 T T DS DH (BIT2) DATA MSB MSB–1 MSB–2 LSB MSB–2 (BIT 0) (BIT1) TPW TCK LSB CLOCK (BIT0) (BIT 1) TES TEH TPW T T ES EH DATA CLOCK CLOCK CLOCK DENB ENABLE DISABLED ENABLED DISABLED (DENB) DATA IS LATCHED ON LOW-TO-HIGH TRANSITION OF DENB DATA IS LATCHED ON HIGH-TO-LOW (NOT TO SCALE) TRANSITION OF DENB (NOT TO SCALE)
Serial Programming Timing Parallel Programming Timing –4– REV. A Document Outline Features Applications Functional Block Diagram Product Description Specifications Timing Specifications Absolute Maximum Ratings Pin Configuration Typical Performance Characteristics Theroy of Operation Input Attentuator and Output 3 dB Step Fixed Gain Amplifier Input and Output Interfaces Noise and Distortion Offset Control Loop Digital Control Basic Connections Input-Output Interface Reducing Gain Sensitivity to Input and Output Impedance Variation Operation from a Single-Sided Source Interfacing to an ADC PCB Layout Considerations Evaluation Board Evaluation Board Software Appendix Characterization Equipment Definitions of Selected Parameters Composite Waveform Assumption Outline Dimensions Ordering Guide Revision History
Frequency = 380 MHz Voltage Gain 38.5 dB Gain Flatness Within ± 20 MHz of 380 MHz ±0.15 dB Noise Figure 7.8 dB Output IP3 f1 = 379.55 MHz, f2 = 380.45 MHz +8.5 dBV rms +8.5 dBm IMD3 f1 = 379.55 MHz, f2 = 380.45 MHz, VOPHI – VOPLO = 1 V p-p composite –47 dBc Harmonic Distortion Second-Order, VOPHI – VOPLO = 1 V p-p –45 dBc Third-Order, VOPHI – VOPLO = 1 V p-p –49 dBc P1dB For ± 1 dB deviation from linear gain +0.5 dBV rms +0.5 dBm Specifications subject to change without notice.
TIMING SPECIFICATIONS SERIAL PROGRAMMING TIMING REQUIREMENTS (VS = 5 V, T = 25
r
C) Parameter Typ Unit
Minimum Clock Pulsewidth (TPW) 10 ns Minimum Clock Period (TCK) 20 ns Minimum Setup Time Data vs. Clock (TDS) 2 ns Minimum Setup Time Data Enable vs. Clock (TES) 2 ns Minimum Hold Time Clock vs. Data Enable (TEH) 2 ns Minimum Hold Time Data vs. Clock (TDH) 4 ns
PARALLEL PROGRAMMING TIMING REQUIREMENTS (VS = 5 V, T = 25
r
C) Parameter Typ Unit
Minimum Setup Time Data Enable vs. Data (TES) 2 ns Minimum Hold Time Data Enable vs. Data (TEH) 2 ns
MSB
Minimum Data Enable Width (TPW) 4 ns
(BIT3) MSB–1 T T DS DH (BIT2) DATA MSB MSB–1 MSB–2 LSB MSB–2 (BIT 0) (BIT1) TPW TCK LSB CLOCK (BIT0) (BIT 1) TES TEH TPW T T ES EH DATA CLOCK CLOCK CLOCK DENB ENABLE DISABLED ENABLED DISABLED (DENB) DATA IS LATCHED ON LOW-TO-HIGH TRANSITION OF DENB DATA IS LATCHED ON HIGH-TO-LOW (NOT TO SCALE) TRANSITION OF DENB (NOT TO SCALE)
Serial Programming Timing Parallel Programming Timing –4– REV. A Document Outline Features Applications Functional Block Diagram Product Description Specifications Timing Specifications Absolute Maximum Ratings Pin Configuration Typical Performance Characteristics Theroy of Operation Input Attentuator and Output 3 dB Step Fixed Gain Amplifier Input and Output Interfaces Noise and Distortion Offset Control Loop Digital Control Basic Connections Input-Output Interface Reducing Gain Sensitivity to Input and Output Impedance Variation Operation from a Single-Sided Source Interfacing to an ADC PCB Layout Considerations Evaluation Board Evaluation Board Software Appendix Characterization Equipment Definitions of Selected Parameters Composite Waveform Assumption Outline Dimensions Ordering Guide Revision History