Datasheet LT6556 (Analog Devices) - 10

LT6556
U U W U APPLICATIO S I FOR ATIO
In order to counteract any peaking in the frequency re- To maintain the LT6556’s channel isolation, it is benefi cial sponse from driving a capacitive load, a series resistance to shield parallel input and parallel output traces using a can be inserted in the line at the output of the part to fl at- ground plane or power supply traces. Vias between top- ten the response. Figure 4 shows the frequency response side and backside metal may be required to maintain a with the same 4cm trace from Figure 3, now with a 10Ω low inductance ground near the part where numerous series resistor inserted near the output pin of the ampli- traces converge. See Figures 7 and 8 for photos of an fi er. Note that using a 10Ω series resistor with a 1k load optimized layout. only decreases the output amplitude by 0.1dB or 1% and has a minimal effect on the bandwidth of the system. See
Single Supply Operation
the graph labeled “Maximum Capacitive Load vs Output Figure 5 illustrates how to use the LT6556 with a single Series Resistor” in the Typical Performance Characteristics supply ranging from 4.5V to 12V. Since the output range is section for more information. comparable to the input range, the DC bias point at the input can be set anywhere between the supplies that will prevent 6 VS = ±5V V the AC-coupled signal from running into the output range OUT = 200mVP-P 4 RL = 1k 4cm TRACE limits. As shown, the DC input level is mid-supply. TA = 25°C 2 The only additional power dissipation in the single supply confi guration is through the resistor bias string at the input 0 4cm TRACE and through any load resistance at the output. In many RS, OUT = 10Ω AMPLITUDE (dB) –2 cases, the output can be used to directly drive other single supply devices without additional coupling and without –4 any resistive load. –60.1 1 10 100 1000 4.5V TO 12V FREQUENCY (MHz) 6556 F04
Figure 4. Response vs Series Output Resistance
5k 22μF IN V+ VIN OUT While the AGND pins on the LT6556 are not connected to 1/3 LT6556 AGND the amplifi er circuitry, tying them to ground or another 5k V– “quiet” node signifi cantly increases channel isolation and is always recommended. The AGND pins do have 6556 F05 ESD protection and therefore should not be connected to potentials outside the power supply range.
Figure 5. Single Supply Confi guration, One Channel Shown
Low ESL/ESR bypass capacitors should be placed as close to the positive and negative supply pins as possible. One
Input Expansion
4700pF ceramic capacitor is recommended for both V+ In applications with more than two inputs per channel, and V– supply busses. Additional 470pF ceramic capacitors multiple LT6556s can be connected directly together at the with minimal trace length on each supply pin will further outputs. Logic circuitry can be used to drive the ⎯E⎯N pins improve AC and transient response as well as channel of each LT6556 to ensure that only one set of channels is isolation. For high current drive and large-signal transient buffered at a time. See Figure 9 for a schematic. applications, additional 1µF to 10µF tantalums should be added on each supply. The smallest value capacitors Since the output impedance of a disabled LT6556 is high, should be placed closest to the package. adding additional channels will not resistively load an 6556f 10