Datasheet LT5524 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | Low Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain |
| 页数 / 页 | 16 / 7 — PI FU CTIO S. EN (Pin 1):. PGA2 (Pin 11):. VCC1 (Pin 2):. PGA3 (Pin 12):. … |
| 文件格式/大小 | PDF / 189 Kb |
| 文件语言 | 英语 |
PI FU CTIO S. EN (Pin 1):. PGA2 (Pin 11):. VCC1 (Pin 2):. PGA3 (Pin 12):. GND. (Pins 3, 4, 7, 8, 13, 14, 17, 18):. IN+ (Pin 5):
该数据表的模型线
文件文字版本
LT5524
U U U PI FU CTIO S EN (Pin 1):
Enable Pin for Amplifier. When the input
PGA2 (Pin 11):
Amplifier PGA Control Input Pin for the 6dB voltage is higher than 3V, the amplifier is turned on. When Attenuation Step (see Programmable Gain table). Input is the input voltage is less than or equal to 0.6V, the amplifier high when the input voltage is greater than 3V. Input is low is turned off. This pin is internally pulled to ground if not when the input voltage is less than or equal to 0.6V. This connected. pin is internally pulled to ground if not connected.
VCC1 (Pin 2):
Power Supply. This pin is internally connected
PGA3 (Pin 12):
Amplifier PGA Control Input Pin for 12dB to VCC2 (Pin 19). Decoupling capacitors (1000pF and 0.1µF Attenuation Step (see Programmable Gain table). Input is for example) may be required in some applications. high when the input voltage is greater than 3V. Input is low when the input voltage is less than or equal to 0.6V. This
GND (Pins 3, 4, 7, 8, 13, 14, 17, 18):
Ground. pin is internally pulled to ground if not connected.
IN+ (Pin 5):
Positive Signal Input Pin with Internal DC
OUT+ (Pin 15):
Positive Amplifier Output. A transformer Bias. with center tap tied to VCC or a choke inductor is recom-
IN– (Pin 6):
Negative Signal Input Pin with Internal DC mended to source the DC quiescent current. Bias.
OUT– (Pin 16):
Negative Amplifier Output. A transformer
PGA0 (Pin 9):
Amplifier PGA Control Input Pin for the 1.5dB with center tap tied to VCC or a choke inductor is recom- Attenuation Step (see Programmable Gain table). Input is mended to source the DC quiescent current. high when the input voltage is greater than 3V. Input is low
V
when the input voltage is less than or equal to 0.6V. This
CC2 (Pin 19):
Power Supply. This pin is internally con- nected to V pin is internally pulled to ground if not connected. CC1 (Pin 2).
NC (Pin 20):
Not Connected.
PGA1 (Pin 10):
Amplifier PGA Control Input Pin for the 3dB Attenuation Step (see Programmable Gain table). Input is
Exposed Pad (Pin 21):
Ground. This pin must be soldered high when the input voltage is greater than 3V. Input is low to the printed circuit board ground plane for good heat when the input voltage is less than or equal to 0.6V. This transfer. pin is internally pulled to ground if not connected.
W BLOCK DIAGRA
LT5524 IN+ ATTENUATOR OUT– 16 5 RIN AMPLIFIER IN– 100Ω OUT+ 6 15 VOLTAGE REGULATOR GAIN CONTROL ENABLE AND BIAS LOGIC CONTROL GND (3, 4, 7, 8 13, 14, 17, 18) V V PGA3 PGA2 PGA1 PGA0 NC EN CC1 CC2 21 2 19 12 11 10 9 20 1 5524 F01
Figure 1. Functional Block Diagram
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U U U PI FU CTIO S EN (Pin 1):
Enable Pin for Amplifier. When the input
PGA2 (Pin 11):
Amplifier PGA Control Input Pin for the 6dB voltage is higher than 3V, the amplifier is turned on. When Attenuation Step (see Programmable Gain table). Input is the input voltage is less than or equal to 0.6V, the amplifier high when the input voltage is greater than 3V. Input is low is turned off. This pin is internally pulled to ground if not when the input voltage is less than or equal to 0.6V. This connected. pin is internally pulled to ground if not connected.
VCC1 (Pin 2):
Power Supply. This pin is internally connected
PGA3 (Pin 12):
Amplifier PGA Control Input Pin for 12dB to VCC2 (Pin 19). Decoupling capacitors (1000pF and 0.1µF Attenuation Step (see Programmable Gain table). Input is for example) may be required in some applications. high when the input voltage is greater than 3V. Input is low when the input voltage is less than or equal to 0.6V. This
GND (Pins 3, 4, 7, 8, 13, 14, 17, 18):
Ground. pin is internally pulled to ground if not connected.
IN+ (Pin 5):
Positive Signal Input Pin with Internal DC
OUT+ (Pin 15):
Positive Amplifier Output. A transformer Bias. with center tap tied to VCC or a choke inductor is recom-
IN– (Pin 6):
Negative Signal Input Pin with Internal DC mended to source the DC quiescent current. Bias.
OUT– (Pin 16):
Negative Amplifier Output. A transformer
PGA0 (Pin 9):
Amplifier PGA Control Input Pin for the 1.5dB with center tap tied to VCC or a choke inductor is recom- Attenuation Step (see Programmable Gain table). Input is mended to source the DC quiescent current. high when the input voltage is greater than 3V. Input is low
V
when the input voltage is less than or equal to 0.6V. This
CC2 (Pin 19):
Power Supply. This pin is internally con- nected to V pin is internally pulled to ground if not connected. CC1 (Pin 2).
NC (Pin 20):
Not Connected.
PGA1 (Pin 10):
Amplifier PGA Control Input Pin for the 3dB Attenuation Step (see Programmable Gain table). Input is
Exposed Pad (Pin 21):
Ground. This pin must be soldered high when the input voltage is greater than 3V. Input is low to the printed circuit board ground plane for good heat when the input voltage is less than or equal to 0.6V. This transfer. pin is internally pulled to ground if not connected.
W BLOCK DIAGRA
LT5524 IN+ ATTENUATOR OUT– 16 5 RIN AMPLIFIER IN– 100Ω OUT+ 6 15 VOLTAGE REGULATOR GAIN CONTROL ENABLE AND BIAS LOGIC CONTROL GND (3, 4, 7, 8 13, 14, 17, 18) V V PGA3 PGA2 PGA1 PGA0 NC EN CC1 CC2 21 2 19 12 11 10 9 20 1 5524 F01
Figure 1. Functional Block Diagram
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