Datasheet LT5524 (Analog Devices) - 8

LT5524
U U W U APPLICATIO S I FOR ATIO Circuit Operation
where: The LT5524 is a high linearity amplifier with high imped- gm is the LT5524 transconductance = 0.15S. ance output (Figure 1). It consists of the following R sections: IN is the LT5524 differential input impedance ≅ 122Ω. Input impedance matching is assumed. • An input variable attenuator “gain-control” block with R 122Ω input impedance OUT is the external differential output impedance as seen by the LT5524’s differential outputs. ROUT should • A differential transconductance amplifier, with enable be distinguished from the actual load impedance, RLOAD, input which will typically be coupled to the LT5524 output by an impedance transformation network. • An internal bias block with internal voltage regulator The power gain as a function of R • A gain control logic block OUT is plotted in Figure 2. The ideal relationship is linear. The curved line indicates The LT5524 amplifier provides amplification with very low the roll-off due to the finite (noninfinite) output resistance distortion using a linearized open-loop architecture. In of the LT5524. contrast with high linearity amplifiers employing negative feedback, the LT5524 offers: 45 • Stable operation for any practical load 40 • A capacitive output reactance (not inductive) that pro- 35 vides peaking free AC response to capacitive loads 30 25 • Exceptional reverse isolation of –100dB at 50MHz and 20 –78dB at 300MHz (package and board leakage limited) GAIN (dB) 15 The LT5524 is a transconductance amplifier and its opera- 10 tion can be understood conceptually as consisting of two 5 IDEAL WITH R steps: First, the input signal voltage is converted to an O 0 20 100 1000 2000 output current. The intermodulation distortion (in dBc) of ROUT (Ω) the LT5524 output current is determined by the input 5524 F02 signal level, and is almost independent of the output load
Figure 2. Power Gain as a Function of R
conditions. Thus, the LT5524’s input IP3 is also nearly
OUT
independent of the output load. The actual available output power (as well as power gain Next, the external output load (ROUT) converts the output and OIP3) will be reduced by losses in the output interface, current to output voltage (or power). The LT5524’s volt- consisting of: age and power gain both increase with increasing ROUT. Accordingly, the output power and output IP3 also in- • The insertion loss of the output impedance transforma- crease with increasing R tion network (for example the transformer insertion OUT. The actual output linearity performance in the application will thus be set by the loss in Figure 6) choice of output load, as well as by the output network. • About –3dB loss if a matching resistor (RMATCH in Figure 6) is used to provide output load impedance
Maximum Gain Calculation
back-matching (for example when driving transmis- The maximum power gain (with the 0dB attenuation step) sion lines) is: G 2 PWR(dB) = 10 • log(gm • RIN • ROUT) 5524f 8