Datasheet ADP2380 (Analog Devices) - 3

制造商Analog Devices
描述20 V, 4 A synchronous Step-Down Regulator with Low-Side Driver
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Data Sheet. ADP2380. SPECIFICATIONS. Table 1. Parameter. Symbol. Test Conditions/Comments. Min. Typ. Max. Unit

Data Sheet ADP2380 SPECIFICATIONS Table 1 Parameter Symbol Test Conditions/Comments Min Typ Max Unit

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Data Sheet ADP2380 SPECIFICATIONS
VIN = 12 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
PVIN PVIN Voltage Range VPVIN 4.5 20 V Quiescent Current IQ No switching 2.2 2.8 3.4 mA Shutdown Current ISHDN EN/SS = GND 85 125 170 µA PVIN Undervoltage Lockout Threshold PVIN rising 4.3 4.5 V PVIN falling 3.7 3.9 V FB FB Regulation Voltage VFB 0°C < TJ < 85°C 0.594 0.6 0.606 V −40°C < TJ < +125°C 0.591 0.6 0.609 V FB Bias Current IFB 0.01 0.1 µA ERROR AMPLIFIER (EA) Transconductance gm 340 470 590 µS EA Source Current ISOURCE 45 60 75 µA EA Sink Current ISINK 45 60 75 µA INTERNAL REGULATOR (VREG) VREG Voltage VVREG VPVIN = 12 V, IVREG = 50 mA 7.7 8 8.4 V Dropout Voltage VPVIN = 12 V, IVREG = 50 mA 350 mV Regulator Current Limit 65 100 130 mA SW High-Side On Resistance1 VBST − VSW = 5 V 44 70 mΩ High-Side Peak Current Limit 4.8 7 9 A Negative Current-Limit Threshold Voltage2 20 mV SW Minimum On Time tMIN_ON 120 155 ns SW Minimum Off Time tMIN_OFF 195 280 ns LOW-SIDE DRIVER (LD) Rising Time2 tR CDL = 2.2 nF; see Figure 17 20 ns Falling Time2 tF CDL = 2.2 nF; see Figure 20 10 ns Sourcing Resistor 4 6.5 Ω Sinking Resistor 2 4.5 Ω BST Bootstrap Voltage VBOOT 4.7 5 5.6 V OSCILLATOR (RT PIN) Switching Frequency fSW RT pin connected to GND 210 290 350 kHz RT pin open 410 540 650 kHz ROSC = 100 kΩ 440 500 560 kHz Switching Frequency Range fSW 250 1400 kHz SYNC Synchronization Range 250 1400 kHz SYNC Minimum Pulse Width 100 ns SYNC Minimum Off Time 100 ns SYNC Input High Voltage 1.3 V SYNC Input Low Voltage 0.4 V EN/SS Enable Threshold 0.5 V Internal Soft Start 1600 Clock cycles SS Pin Pull-Up Current ISS_UP 2.4 3.2 3.6 µA Rev. 0 | Page 3 of 28 Document Outline Features Applications Typical Applications Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Information ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Functional Block Diagram Theory of Operation Control Scheme Internal Regulator (VREG) Bootstrap Circuitry Low-Side Driver Oscillator Synchronization Enable and Soft Start Power Good Peak Current-Limit and Short-Circuit Protection Overvoltage Protection (OVP) Undervoltage Lockout (UVLO) Thermal Shutdown Applications Information Input Capacitor Selection Output Voltage Setting Voltage Conversion Limitations Inductor Selection Output Capacitor Selection Low-Side Power Device Selection Programming Input Voltage UVLO Compensation Design Compensation Network Between COMP and GND Compensation Network Between COMP and FB ADIsimPower Design Tool Design Example Output Voltage Setting Frequency Setting Inductor Selection Output Capacitor Selection Low-Side MOSFET Selection Compensation Components Soft Start Time Program Input Capacitor Selection Recommended External Components Circuit Board Layout Recommendations Typical Applications Circuits Outline Dimensions Ordering Guide