Datasheet ADP2116 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | Configurable, Dual 3 A/Single 6 A, Synchronous, Step-Down DC-to-DC Regulator |
| 页数 / 页 | 36 / 9 — Data Sheet. ADP2116. LINE AND LOAD REGULATION. 0.25. 0.20. % 0.15. 0.15. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 2.9 Mb |
| 文件语言 | 英语 |
Data Sheet. ADP2116. LINE AND LOAD REGULATION. 0.25. 0.20. % 0.15. 0.15. D (. E 0.10. 0.10. A 0.05. 0.05. –0.05. RO R. RRO. E –0.10. –0.10. OU –0.15. –0.15
该数据表的模型线
文件文字版本
Data Sheet ADP2116 LINE AND LOAD REGULATION 0.25 0.25 0.20 0.20 ) ) % 0.15 % 0.15 D ( D ( E 0.10 E 0.10 IZ IZ L L A 0.05 A M 0.05 M R R 0 NO 0 NO R, R, –0.05 –0.05 RO R RRO E –0.10 E 1 –0.10 2 T T OU –0.15 OU V –0.15 V –0.20 –0.20 –0.25 –0.25 0 0.5 1.0 1.5 2.0 2.5 3.0
1 08
0 0.5 1.0 1.5 2.0 2.5 3.0
0 01 6- 6-
LOAD CURRENT (A)
43
LOAD CURRENT (A)
43 08 08 Figure 8. Load Regulation, Channel 1: VIN = 5 V, fSW = 600 kHz, and TA = 25°C Figure 11. Load Regulation, Channel 2: VIN = 5 V, fSW = 600 kHz, and TA = 25°C
0.5 0.5 0.4 0.4 ) ) % 0.3 % 0.3 D ( D ( E 0.2 E 0.2 IZ IZ AL 0.1 AL 0.1 RM RM 0 0 , NO , NO R R –0.1 –0.1 RO RO R R E –0.2 E 1 –0.2 T 2 T OU –0.3 V OUV –0.3 –0.4 –0.4 –0.5 –0.5 3.5 4.0 4.5 5.0 5.5
09
2.5 3.0 3.5 4.0 4.5 5.0 5.5
12 -0 0 6-
V
36
IN (V) VIN (V)
43 084 08 Figure 9. Line Regulation, Channel 1: Load Current = 3 A and fSW = 600 kHz Figure 12. Line Regulation, Channel 2: Load Current = 3 A and fSW = 600 kHz
1.00 1.00 0.75 0.75 0.50 0.50 ) ) % 0.25 % 0.25 R ( R ( V V RO IN = 5.5V, NO LOAD IN = 5.5V, NO LOAD R 0 RRO 0 E 1 E T 2 T V OU –0.25 V –0.25 IN = 2.75V, 2A LOAD V IN = 2.75V, 3A LOAD OUV –0.50 –0.50 –0.75 –0.75 –1.00 –1.00 –50 –25 0 25 50 75 100 125
10 3 0
–50 –25 0 25 50 75 100 125
01 6- 6-
TEMPERATURE (°C)
843
TEMPERATURE (°C)
43 0 08 Figure 10. Output Voltage Error vs. Temperature, Figure 13. Output Voltage Error vs. Temperature, Channel 1: VOUT = 0.6 V and fSW = 600 kHz Channel 2: VOUT = 1.5 V and fSW = 600 kHz Rev. B | Page 9 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS LINE AND LOAD REGULATION SUPPLY CURRENT LOAD TRANSIENT RESPONSE BASIC FUNCTIONALITY BODE PLOTS SIMPLIFIED BLOCK DIAGRAM THEORY OF OPERATION CONTROL ARCHITECTURE UNDERVOLTAGE LOCKOUT (UVLO) ENABLE/DISABLE CONTROL SOFT START POWER GOOD PULSE SKIP MODE HICCUP MODE CURRENT LIMIT THERMAL OVERLOAD PROTECTION MAXIMUM DUTY CYCLE OPERATION SYNCHRONIZATION CONVERTER CONFIGURATION SELECTING THE OUTPUT VOLTAGE SETTING THE OSCILLATOR FREQUENCY SYNCHRONIZATION AND CLKOUT OPERATION MODE CONFIGURATION EXTERNAL COMPONENTS SELECTION ADIsimPower DESIGN TOOL INPUT CAPACITOR SELECTION VDD RC FILTER INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION CONTROL LOOP COMPENSATION DESIGN EXAMPLE CHANNEL 1 CONFIGURATION AND COMPONENTS SELECTION CHANNEL 2 CONFIGURATION AND COMPONENTS SELECTION SYSTEM CONFIGURATION APPLICATION CIRCUITS POWER DISSIPATION AND THERMAL CONSIDERATIONS CIRCUIT BOARD LAYOUT RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE
1 08
0 0.5 1.0 1.5 2.0 2.5 3.0
0 01 6- 6-
LOAD CURRENT (A)
43
LOAD CURRENT (A)
43 08 08 Figure 8. Load Regulation, Channel 1: VIN = 5 V, fSW = 600 kHz, and TA = 25°C Figure 11. Load Regulation, Channel 2: VIN = 5 V, fSW = 600 kHz, and TA = 25°C
0.5 0.5 0.4 0.4 ) ) % 0.3 % 0.3 D ( D ( E 0.2 E 0.2 IZ IZ AL 0.1 AL 0.1 RM RM 0 0 , NO , NO R R –0.1 –0.1 RO RO R R E –0.2 E 1 –0.2 T 2 T OU –0.3 V OUV –0.3 –0.4 –0.4 –0.5 –0.5 3.5 4.0 4.5 5.0 5.5
09
2.5 3.0 3.5 4.0 4.5 5.0 5.5
12 -0 0 6-
V
36
IN (V) VIN (V)
43 084 08 Figure 9. Line Regulation, Channel 1: Load Current = 3 A and fSW = 600 kHz Figure 12. Line Regulation, Channel 2: Load Current = 3 A and fSW = 600 kHz
1.00 1.00 0.75 0.75 0.50 0.50 ) ) % 0.25 % 0.25 R ( R ( V V RO IN = 5.5V, NO LOAD IN = 5.5V, NO LOAD R 0 RRO 0 E 1 E T 2 T V OU –0.25 V –0.25 IN = 2.75V, 2A LOAD V IN = 2.75V, 3A LOAD OUV –0.50 –0.50 –0.75 –0.75 –1.00 –1.00 –50 –25 0 25 50 75 100 125
10 3 0
–50 –25 0 25 50 75 100 125
01 6- 6-
TEMPERATURE (°C)
843
TEMPERATURE (°C)
43 0 08 Figure 10. Output Voltage Error vs. Temperature, Figure 13. Output Voltage Error vs. Temperature, Channel 1: VOUT = 0.6 V and fSW = 600 kHz Channel 2: VOUT = 1.5 V and fSW = 600 kHz Rev. B | Page 9 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS LINE AND LOAD REGULATION SUPPLY CURRENT LOAD TRANSIENT RESPONSE BASIC FUNCTIONALITY BODE PLOTS SIMPLIFIED BLOCK DIAGRAM THEORY OF OPERATION CONTROL ARCHITECTURE UNDERVOLTAGE LOCKOUT (UVLO) ENABLE/DISABLE CONTROL SOFT START POWER GOOD PULSE SKIP MODE HICCUP MODE CURRENT LIMIT THERMAL OVERLOAD PROTECTION MAXIMUM DUTY CYCLE OPERATION SYNCHRONIZATION CONVERTER CONFIGURATION SELECTING THE OUTPUT VOLTAGE SETTING THE OSCILLATOR FREQUENCY SYNCHRONIZATION AND CLKOUT OPERATION MODE CONFIGURATION EXTERNAL COMPONENTS SELECTION ADIsimPower DESIGN TOOL INPUT CAPACITOR SELECTION VDD RC FILTER INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION CONTROL LOOP COMPENSATION DESIGN EXAMPLE CHANNEL 1 CONFIGURATION AND COMPONENTS SELECTION CHANNEL 2 CONFIGURATION AND COMPONENTS SELECTION SYSTEM CONFIGURATION APPLICATION CIRCUITS POWER DISSIPATION AND THERMAL CONSIDERATIONS CIRCUIT BOARD LAYOUT RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE