Datasheet ADP5020 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | Power Management Unit for Imaging Modules |
| 页数 / 页 | 28 / 1 — Power Management Unit. for Imaging Modules. ADP5020. FEATURES. TYPICAL … |
| 修订版 | A |
| 文件格式/大小 | PDF / 1.1 Mb |
| 文件语言 | 英语 |
Power Management Unit. for Imaging Modules. ADP5020. FEATURES. TYPICAL APPLICATIONS CIRCUIT. Input voltage range: 2.4 V to 5.5 V
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文件文字版本
Power Management Unit for Imaging Modules ADP5020 FEATURES TYPICAL APPLICATIONS CIRCUIT V Input voltage range: 2.4 V to 5.5 V IN 2.4V TO 5.5V Low standby current: 1 μA VDD1 SW1 Switching frequency: 3 MHz 10µF 2.2µH I2C interface VOUT1 VDD2 VOUT1 2.5V TO 3.7V Synchronous Buck 1 regulator: 600 mA VOUT1 Synchronous Buck 2 regulator: 250 mA 10µF VDD3 PGND1 Low dropout regulator (LDO): 150 mA VOUT2 Internal compensation ADP5020 2.2µH 1.1V TO 1.8V VDDA SW2 Internal soft start 1µF V 4.7µF VOUT2 Thermal shutdown DD_IO 1.7V TO 3.6V 20-lead 4 mm × 4 mm LFCSP VDD_IO PGND2 VOUT3 10kΩ 10kΩ APPLICATIONS 0.1µF 1.8V TO 3.3V VOUT3 Digital cameras, handsets 1µF SDA Mobile TVs SCL EXT. FREQ XSHTDN SYNC 9.6/19.2MHz EN/GPIO DGND AGND
1 -00 774 07 Figure 1.
GENERAL DESCRIPTION
The ADP5020 provides a highly integrated power solution that The ADP5020 provides high performance, reduces component includes all of the power circuits necessary for a digital imaging count and size, and is lower in cost when compared to conven- module. It comprises two step-down dc-to-dc converters, one tional designs. LDO, and a power sequence controller. All dc-to-dc converters The ADP5020 runs on input voltage from 2.4 V to 5.5 V and integrate power pMOSFETs and nMOSFETs, making the system supports one-cell lithium-ion (Li+) batteries. The high perfor- simpler and more compact and reducing the cost. The ADP5020 mance LDO maximizes noise suppression. The ADP5020 can be has digitally programmed output voltages and buck converters activated via an I2C® interface or through a dedicated enable input. that can source up to 600 mA. A fixed frequency operation of During logic-controlled shutdown, the input is disconnected 3 MHz enables the use of tiny inductors and capacitors. The buck from the output source, and the part draws 1 μA typical from converters use a voltage mode, constant-frequency PWM control the input source. Other key features include undervoltage lockout scheme, and the synchronous rectification is implemented to to prevent deep-battery discharge and soft start to prevent input reduce the power loss. The Buck 1 regulator operates at up to current overshoot at startup. The ADP5020 is available in a 93% efficiency. 20-lead LFCSP.
Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS TYPICAL APPLICATIONS CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS SWITCHING SPECIFICATIONS DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 1 REGULATOR DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 2 REGULATOR VOUT3 SPECIFICATIONS, LOW DROPOUT (LDO) REGULATOR I2C TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Thermal Data ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CIRCUIT OPERATION INTERNAL COMPENSATION CURRENT LIMITING AND SHORT-CIRCUIT PROTECTION SYNCHRONIZATION I2C INTERFACE UNDERVOLTAGE LOCKOUT THERMAL SHUTDOWN CONTROL REGISTERS DEVICE ADDRESS REGISTER MAP REGISTER DESCRIPTIONS User Accessible Registers POWER-UP/POWER-DOWN SEQUENCE SEQUENCER DEFAULT POWER-ON SEQUENCE WITH EN PIN Activation Waveforms POWER-ON SEQUENCE USING THE I2C INTERFACE POWER-UP/POWER-DOWN STATE FLOW APPLICATIONS INFORMATION POWER GOOD STATUS XSHTDN LOGIC COMPONENTS SELECTION Buck Inductor Input Capacitor Selection Output Capacitor Selection LDO INPUT FILTER LAYOUT RECOMMENDATIONS APPLICATIONS SCHEMATIC PCB BOARD LAYOUT RECOMMENDATIONS EXTERNAL COMPONENT LIST OUTLINE DIMENSIONS ORDERING GUIDE
1 -00 774 07 Figure 1.
GENERAL DESCRIPTION
The ADP5020 provides a highly integrated power solution that The ADP5020 provides high performance, reduces component includes all of the power circuits necessary for a digital imaging count and size, and is lower in cost when compared to conven- module. It comprises two step-down dc-to-dc converters, one tional designs. LDO, and a power sequence controller. All dc-to-dc converters The ADP5020 runs on input voltage from 2.4 V to 5.5 V and integrate power pMOSFETs and nMOSFETs, making the system supports one-cell lithium-ion (Li+) batteries. The high perfor- simpler and more compact and reducing the cost. The ADP5020 mance LDO maximizes noise suppression. The ADP5020 can be has digitally programmed output voltages and buck converters activated via an I2C® interface or through a dedicated enable input. that can source up to 600 mA. A fixed frequency operation of During logic-controlled shutdown, the input is disconnected 3 MHz enables the use of tiny inductors and capacitors. The buck from the output source, and the part draws 1 μA typical from converters use a voltage mode, constant-frequency PWM control the input source. Other key features include undervoltage lockout scheme, and the synchronous rectification is implemented to to prevent deep-battery discharge and soft start to prevent input reduce the power loss. The Buck 1 regulator operates at up to current overshoot at startup. The ADP5020 is available in a 93% efficiency. 20-lead LFCSP.
Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS TYPICAL APPLICATIONS CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS SWITCHING SPECIFICATIONS DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 1 REGULATOR DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 2 REGULATOR VOUT3 SPECIFICATIONS, LOW DROPOUT (LDO) REGULATOR I2C TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Thermal Data ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CIRCUIT OPERATION INTERNAL COMPENSATION CURRENT LIMITING AND SHORT-CIRCUIT PROTECTION SYNCHRONIZATION I2C INTERFACE UNDERVOLTAGE LOCKOUT THERMAL SHUTDOWN CONTROL REGISTERS DEVICE ADDRESS REGISTER MAP REGISTER DESCRIPTIONS User Accessible Registers POWER-UP/POWER-DOWN SEQUENCE SEQUENCER DEFAULT POWER-ON SEQUENCE WITH EN PIN Activation Waveforms POWER-ON SEQUENCE USING THE I2C INTERFACE POWER-UP/POWER-DOWN STATE FLOW APPLICATIONS INFORMATION POWER GOOD STATUS XSHTDN LOGIC COMPONENTS SELECTION Buck Inductor Input Capacitor Selection Output Capacitor Selection LDO INPUT FILTER LAYOUT RECOMMENDATIONS APPLICATIONS SCHEMATIC PCB BOARD LAYOUT RECOMMENDATIONS EXTERNAL COMPONENT LIST OUTLINE DIMENSIONS ORDERING GUIDE