Datasheet LTC3564 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 2.25MHz, 1.25A Synchronous Step-Down Regulator |
| 页数 / 页 | 20 / 7 — PI FU CTIO S (S5/DCB). VFB (Pin 1/Pin 4) :. RUN (Pin 5/Pin 6):. GND (Pin … |
| 文件格式/大小 | PDF / 269 Kb |
| 文件语言 | 英语 |
PI FU CTIO S (S5/DCB). VFB (Pin 1/Pin 4) :. RUN (Pin 5/Pin 6):. GND (Pin 2/NA):. VIN (Pin 3/Pin 3):. PGND (NA/Pin 2):
该数据表的模型线
文件文字版本
LTC3564
U U U PI FU CTIO S (S5/DCB) VFB (Pin 1/Pin 4) :
Feedback Pin. Receives the feedback
RUN (Pin 5/Pin 6):
Run Control Input. Forcing this pin voltage from an external resistive divider across the out- above 1.5V enables the part. Forcing this pin below 0.3V put. shuts down the device. In shutdown, all functions are disabled drawing <1μA supply current. Do not leave RUN
GND (Pin 2/NA):
Ground Pin. floating.
VIN (Pin 3/Pin 3):
Main Supply Pin. Must be closely
PGND (NA/Pin 2):
Main Power Ground Pin. Connect to the decoupled to GND, Pin 2, with a 10μF or greater ceramic (–) terminal of C capacitor. OUT, and (–) terminal of CIN.
SGND (NA/Pins 5, 7):
The Signal Ground Pin. All small
SW (Pin 4/Pin 1):
Switch Node Connection to Inductor. signal components and compensation components should This pin connects to the drains of the internal main and be connected to this ground (see Board Layout Consider- synchronous power MOSFET switches. ations.)
U U W FU CTIO AL DIAGRA
SLOPE COMP 0.65V OSC OSC FREQ VIN SHIFT – VFB + – SLEEP + 0.6V RSENSE 0.52V + – + I – EA COMP BURST S Q R Q SWITCHING RS LATCH LOGIC VIN AND ANTI- BLANKING SHOOT- CIRCUIT THRU SW RUN 0.6V REF + SHUTDOWN IRCMP– GND 3564 FD 3564f 7
U U U PI FU CTIO S (S5/DCB) VFB (Pin 1/Pin 4) :
Feedback Pin. Receives the feedback
RUN (Pin 5/Pin 6):
Run Control Input. Forcing this pin voltage from an external resistive divider across the out- above 1.5V enables the part. Forcing this pin below 0.3V put. shuts down the device. In shutdown, all functions are disabled drawing <1μA supply current. Do not leave RUN
GND (Pin 2/NA):
Ground Pin. floating.
VIN (Pin 3/Pin 3):
Main Supply Pin. Must be closely
PGND (NA/Pin 2):
Main Power Ground Pin. Connect to the decoupled to GND, Pin 2, with a 10μF or greater ceramic (–) terminal of C capacitor. OUT, and (–) terminal of CIN.
SGND (NA/Pins 5, 7):
The Signal Ground Pin. All small
SW (Pin 4/Pin 1):
Switch Node Connection to Inductor. signal components and compensation components should This pin connects to the drains of the internal main and be connected to this ground (see Board Layout Consider- synchronous power MOSFET switches. ations.)
U U W FU CTIO AL DIAGRA
SLOPE COMP 0.65V OSC OSC FREQ VIN SHIFT – VFB + – SLEEP + 0.6V RSENSE 0.52V + – + I – EA COMP BURST S Q R Q SWITCHING RS LATCH LOGIC VIN AND ANTI- BLANKING SHOOT- CIRCUIT THRU SW RUN 0.6V REF + SHUTDOWN IRCMP– GND 3564 FD 3564f 7