Datasheet ADP1876 (Analog Devices) - 4

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ADP1876 Data Sheet SPECIFICATIONS
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control. VIN = 12 V. The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TA = 25°C.
Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY Input Voltage VIN 2.75 20 V Undervoltage Lockout Threshold INUVLO VIN rising 2.45 2.6 2.75 V VIN falling 2.4 2.5 2.6 Undervoltage Lockout Hysteresis 0.1 V Quiescent Current IIN EN1 = EN2 = VIN = 12 V, VFB = VCCO 4.5 5.9 mA (no switching) Shutdown Current IIN_SD EN1 = EN2 = GND, VIN = 5.5 V or 20 V 100 200 µA ERROR AMPLIFIER FB Input Bias Current IFB −100 +1 +100 nA Transconductance gm Sink or source 1 µA 385 550 715 µS TRK1 Input Bias Current ITRK 0 V < VTRK1 < 1.5 V −100 +1 +100 nA CURRENT SENSE AMPLIFIER GAIN ACS Gain resistor connected to DLx, 2.4 3 3.6 V/V RCSG = 47 kΩ ± 5% Gain resistor connected to DLx, 5.2 6 6.9 V/V RCSG = 22 kΩ ± 5% Default setting, RCSG = open 10.5 12 13.5 V/V Gain resistor connected to DLx, 20.5 24 26.5 V/V RCSG = 100 kΩ ± 5% OUTPUT CHARACTERICTISTICS Feedback Accuracy Voltage VFB TJ = −40°C to +85°C, VFB = 0.6 V −0.85% +0.6 +0.85% V TJ = −40°C to +125°C, VFB = 0.6 V −1.5% +0.6 +1.5% V Line Regulation of PWM ΔVFB/ΔVIN ±0.015 %/V Load Regulation of PWM ΔVFB/ΔVCOMP VCOMP range 0.9 V to 2.2 V ±0.3 % Oscillator Frequency fOSC 475 600 690 kHz LINEAR REGULATOR VCCO VCCO Output Voltage TA = 25°C, IVCCO = 100 mA 4.8 5.0 5.18 V TJ = −40°C to +125°C 4.7 5.0 5.3 V VCCO Load Regulation IVCCO = 0 mA to 100 mA, 35 mV VCCO Line Regulation VIN = 5.5 V to 20 V, IVCCO = 20 mA 10 mV VCCO Short-Circuit Current1 VCCO < 0.5 V 370 400 mA VIN to VCCO Dropout Voltage2 VDROPOUT IVCCO = 100 mA, VIN ≤ 5 V 0.33 V LOGIC INPUTS EN1, EN2 Threshold EN1/EN2 rising 0.57 0.63 0.68 V EN1, EN2 Hysteresis 0.03 V EN1, EN2 Input Leakage Current IEN VIN = 2.75 V to 20 V 1 200 nA GATE DRIVERS (DHx, DLx PINS) DHx Rise Time CDH = 3 nF, VBST − VSW = 5 V 16 ns DHx Fall Time CDH = 3 nF, VBST − VSW = 5 V 14 ns DLx Rise Time CDL = 3 nF 16 ns DLx Fall Time CDL = 3 nF 14 ns DHx to DLx Dead Time External 3 nF capacitor is connected to 25 ns DHx and DLx Rev. B | Page 4 of 24 Document Outline FEATURES APPLICATIONS TYPICAL OPERATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INDEPENDENT LOW DROPOUT LINEAR REGULATOR CONTROLLER ARCHITECTURE Synchronous Rectifier and Dead Time INPUT UNDERVOLTAGE LOCKOUT INTERNAL LINEAR REGULATOR (VCCO) OVERVOLTAGE PROTECTION POWER GOOD SHORT-CIRCUIT AND CURRENT-LIMIT PROTECTION SHUTDOWN CONTROL THERMAL OVERLOAD PROTECTION APPLICATIONS INFORMATION INDEPENDENT LOW DROPOUT LINEAR REGULATOR SETTING THE OUTPUT VOLTAGE OF THE CONTROLLER SOFT START SETTING THE CURRENT LIMIT ACCURATE CURRENT-LIMIT SENSING SETTING THE SLOPE COMPENSATION SETTING THE CURRENT SENSE GAIN INPUT CAPACITOR SELECTION INPUT FILTER BOOST CAPACITOR SELECTION INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION MOSFET SELECTION LOOP COMPENSATION SWITCHING NOISE AND OVERSHOOT REDUCTION PCB LAYOUT GUIDELINE TYPICAL APPLICATIONS CIRCUIT PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE