Datasheet ADSP-BF592 (Analog Devices) - 5

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ADSP-BF592 MEMORY ARCHITECTURE Custom ROM (Optional)
The Blackfin processor views memory as a single unified The on-chip L1 Instruction ROM on the ADSP-BF592 may be 4G byte address space, using 32-bit addresses. All resources, customized to contain user code with the following features: including internal memory and I/O control registers, occupy • 64K bytes of L1 Instruction ROM available for custom code separate sections of this common address space. See Figure 3. • Ability to restrict access to all or specific segments of the The core-accessible L1 memory system is high performance on-chip ROM internal memory that operates at the core clock frequency. The external bus interface unit (EBIU) provides access to the boot Customers wishing to customize the on-chip ROM for their ROM. own application needs should contact ADI sales for more infor- mation on terms and conditions and details on the technical The memory DMA controller provides high bandwidth data- implementation. movement capability. It can perform block transfers of code or data between the L1 Instruction SRAM and L1 Data SRAM
I/O Memory Space
memory spaces. The processor does not define a separate I/O space. All resources are mapped through the flat 32-bit address space.
0xFFFF FFFF
On-chip I/O devices have their control registers mapped into
CORE MEMORY MAPPED REGISTERS (2M BYTES)
memory-mapped registers (MMRs) at addresses near the top of
0xFFE0 0000 SYSTEM MEMORY MAPPED REGISTERS (2M BYTES)
the 4G byte address space. These are separated into two smaller
0xFFC0 0000
blocks, one which contains the control MMRs for all core func-
RESERVED 0xFFB0 1000
tions, and the other which contains the registers needed for
L1 SCRATCHPAD RAM (4K BYTES) 0xFFB0 0000
setup and control of the on-chip peripherals outside of the core.
RESERVED
The MMRs are accessible only in supervisor mode and appear
0xFFA2 0000 L1 INSTRUCTION ROM (64K BYTES)
as reserved space to on-chip peripherals.
0xFFA1 0000 RESERVED 0xFFA0 8000 Booting from ROM L1 INSTRUCTION BANK B SRAM (16K BYTES) 0xFFA0 4000
The processor contains a small on-chip boot kernel, which con-
L1 INSTRUCTION BANK A SRAM (16K BYTES) 0xFFA0 0000
figures the appropriate peripheral for booting. If the processor is
RESERVED 0xFF80 8000
configured to boot from boot ROM memory space, the proces-
DATA SRAM (32K BYTES)
sor starts executing from the on-chip boot ROM. For more
0xFF80 0000 RESERVED
information, see Booting Modes on Page 11.
0xEF00 1000 BOOT ROM (4K BYTES) 0xEF00 0000 EVENT HANDLING RESERVED 0x0000 0000
The event controller on the processor handles all asynchronous and synchronous events to the processor. The processor Figure 3. Internal/External Memory Map provides event handling that supports both nesting and prioriti- zation. Nesting allows multiple event service routines to be
Internal (Core-Accessible) Memory
active simultaneously. Prioritization ensures that servicing of a The processor has three blocks of core-accessible memory, pro- higher-priority event takes precedence over servicing of a lower- viding high bandwidth access to the core. priority event. The controller provides support for five different The first block is the L1 instruction memory, consisting of types of events: 32K bytes SRAM. This memory is accessed at full processor • Emulation – An emulation event causes the processor to speed. enter emulation mode, allowing command and control of The second core-accessible memory block is the L1 data mem- the processor via the JTAG interface. ory, consisting of 32K bytes. This memory block is accessed at • RESET – This event resets the processor. full processor speed. • Nonmaskable Interrupt (NMI) – The NMI event can be The third memory block is a 4K byte L1 scratchpad SRAM, generated by the software watchdog timer or by the NMI which runs at the same speed as the other L1 memories. input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shut-
L1 Utility ROM
down of the system. The L1 instruction ROM contains utility ROM code. This includes the TMK (VDK core), C run-time libraries, and DSP libraries. See the VisualDSP++ documentation for more information. Rev. B | Page 5 of 44 | July 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory L1 Utility ROM Custom ROM (Optional) I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Watchdog Timer Timers Serial Ports Serial Peripheral Interface (SPI) Ports UART Port Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF592 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 64-Lead LFCSP Lead Assignment Outline Dimensions Automotive Products Ordering Guide