Datasheet ADSP-BF522, ADSP-BF523, ADSP-BF524, ADSP-BF525, ADSP-BF526, ADSP-BF527 (Analog Devices) - 6

link to page 18
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
The SDRAM controller can be programmed to interface to up ID, MAC address, etc. Hence, generic parts can be shipped, to 128M bytes of SDRAM. A separate row can be open for each which are then programmed and protected by the developer SDRAM internal bank and the SDRAM controller supports up within this non-volatile memory. to 4 internal SDRAM banks, improving overall performance.
I/O Memory Space
The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing The processor does not define a separate I/O space. All requirements for a wide variety of devices. Each bank occupies a resources are mapped through the flat 32-bit address space. 1M byte segment regardless of the size of the devices used, so On-chip I/O devices have their control registers mapped into that these banks are only contiguous if each is fully populated memory-mapped registers (MMRs) at addresses near the top of with 1M byte of memory. the 4G byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all core func-
NAND Flash Controller (NFC)
tions, and the other which contains the registers needed for The ADSP-BF52x processors provide a NAND flash controller setup and control of the on-chip peripherals outside of the core. (NFC). NAND flash devices provide high-density, low-cost The MMRs are accessible only in supervisor mode and appear memory. However, NAND flash devices also have long random as reserved space to on-chip peripherals. access times, invalid blocks, and lower reliability over device
Booting
lifetimes. Because of this, NAND flash is often used for read- only code storage. In this case, all DSP code can be stored in The processor contains a small on-chip boot kernel, which con- NAND flash and then transferred to a faster memory (such as figures the appropriate peripheral for booting. If the processor is SDRAM or SRAM) before execution. Another common use of configured to boot from boot ROM memory space, the proces- NAND flash is for storage of multimedia files or other large data sor starts executing from the on-chip boot ROM. For more segments. In this case, a software file system may be used to information, see Booting Modes on Page 18. manage reading and writing of the NAND flash device. The file
Event Handling
system selects memory segments for storage with the goal of avoiding bad blocks and equally distributing memory accesses The event controller on the processor handles all asynchronous across all address locations. Hardware features of the NFC and synchronous events to the processor. The processor pro- include: vides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to • Support for page program, page read, and block erase of be active simultaneously. Prioritization ensures that servicing of NAND flash devices, with accesses aligned to page a higher-priority event takes precedence over servicing of a boundaries. lower-priority event. The controller provides support for five • Error checking and correction (ECC) hardware that facili- different types of events: tates error detection and correction. • Emulation — An emulation event causes the processor to • A single 8-bit external bus interface for commands, enter emulation mode, allowing command and control of addresses, and data. the processor via the JTAG interface. • Support for SLC (single level cell) NAND flash devices • RESET — This event resets the processor. unlimited in size, with page sizes of 256 and 512 bytes. • Nonmaskable Interrupt (NMI) — The NMI event can be Larger page sizes can be supported in software. generated by the software watchdog timer or by the NMI • Capability of releasing external bus interface pins during input signal to the processor. The NMI event is frequently long accesses. used as a power-down indicator to initiate an orderly shut- • Support for internal bus requests of 16 bits. down of the system. • DMA engine to transfer data between internal memory and • Exceptions — Events that occur synchronously to program NAND flash device. flow (in other words, the exception is taken before the instruction is allowed to complete). Conditions such as
One-Time Programmable Memory
data alignment violations and undefined instructions cause The processor has 64K bits of one-time programmable non- exceptions. volatile memory that can be programmed by the developer only • Interrupts — Events that occur asynchronously to program one time. It includes the array and logic to support read access flow. They are caused by input signals, timers, and other and programming. Additionally, its pages can be write peripherals, as well as by an explicit software instruction. protected. Each event type has an associated register to hold the return OTP enables developers to store both public and private data address and an associated return-from-event instruction. When on-chip. In addition to storing public and private key data for an event is triggered, the state of the processor is saved on the applications requiring security, it also allows developers to store supervisor stack. completely user-definable data such as customer ID, product The processor event controller consists of two stages, the core event controller (CEC) and the system interrupt controller (SIC). The core event controller works with the system interrupt Rev. D | Page 6 of 88 | July 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory NAND Flash Controller (NFC) One-Time Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports Serial Peripheral Interface (SPI) Port UART Ports TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode USB On-The-Go Dual-Role Device Controller Code Security with Lockbox Secure Technology Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage Regulation ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Lockbox Secure Technology Disclaimer Signal Descriptions Specifications Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Clock Related Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Clock Related Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing NAND Flash Controller Interface Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing HOSTDP A/C Timing- Host Read Cycle HOSTDP A/C Timing- Host Write Cycle 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 289-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide