Datasheet ADSP-BF522, ADSP-BF523, ADSP-BF524, ADSP-BF525, ADSP-BF526, ADSP-BF527 (Analog Devices) - 7

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ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
controller to prioritize and control all system events. Conceptu-
Table 2. Core Event Controller (CEC)
ally, interrupts from the peripherals enter into the SIC and are then routed directly into the general-purpose interrupts of the
Priority
CEC.
(0 is Highest) Event Class EVT Entry
0 E mulation/Test Control EMU
Core Event Controller (CEC)
1 RESET RST The CEC supports nine general-purpose interrupts (IVG15–7), 2 Nonmaskable Interrupt NMI in addition to the dedicated interrupt and exception events. Of 3 Exception EVX these general-purpose interrupts, the two lowest-priority interrupts (IVG15–14) are recommended to be reserved for 4 Reserved — software interrupt handlers, leaving seven prioritized interrupt 5 Hardware Error IVHW inputs to support the peripherals of the processor. Table 2 6 Core Timer IVTMR describes the inputs to the CEC, identifies their names in the 7 General-Purpose Interrupt 7 IVG7 event vector table (EVT), and lists their priorities. 8 General-Purpose Interrupt 8 IVG8
System Interrupt Controller (SIC)
9 General-Purpose Interrupt 9 IVG9 The system interrupt controller provides the mapping and rout- 10 General-Purpose Interrupt 10 IVG10 ing of events from the many peripheral interrupt sources to the 11 General-Purpose Interrupt 11 IVG11 prioritized general-purpose interrupt inputs of the CEC. 12 General-Purpose Interrupt 12 IVG12 Although the processor provides a default mapping, the user 13 General-Purpose Interrupt 13 IVG13 can alter the mappings and priorities of interrupt events by writ- ing the appropriate values into the interrupt assignment 14 General-Purpose Interrupt 14 IVG14 registers (SIC_IARx). Table 3 describes the inputs into the SIC 15 General-Purpose Interrupt 15 IVG15 and the default mappings into the CEC.
Table 3. System Interrupt Controller (SIC) General Purpose Default Peripheral Interrupt Event Interrupt (at RESET) Peripheral Interrupt ID Core Interrupt ID SIC Registers
PLL Wakeup Interrupt IVG7 0 0 IAR0 IMASK0, ISR0, IWR0 DMA Error 0 (generic) IVG7 1 0 IAR0 IMASK0, ISR0, IWR0 DMAR0 Block Interrupt IVG7 2 0 IAR0 IMASK0, ISR0, IWR0 DMAR1 Block Interrupt IVG7 3 0 IAR0 IMASK0, ISR0, IWR0 DMAR0 Overflow Error IVG7 4 0 IAR0 IMASK0, ISR0, IWR0 DMAR1 Overflow Error IVG7 5 0 IAR0 IMASK0, ISR0, IWR0 PPI Error IVG7 6 0 IAR0 IMASK0, ISR0, IWR0 MAC Status IVG7 7 0 IAR0 IMASK0, ISR0, IWR0 SPORT0 Status IVG7 8 0 IAR1 IMASK0, ISR0, IWR0 SPORT1 Status IVG7 9 0 IAR1 IMASK0, ISR0, IWR0 Reserved IVG7 10 0 IAR1 IMASK0, ISR0, IWR0 Reserved IVG7 11 0 IAR1 IMASK0, ISR0, IWR0 UART0 Status IVG7 12 0 IAR1 IMASK0, ISR0, IWR0 UART1 Status IVG7 13 0 IAR1 IMASK0, ISR0, IWR0 RTC IVG8 14 1 IAR1 IMASK0, ISR0, IWR0 DMA Channel 0 (PPI/NFC) IVG8 15 1 IAR1 IMASK0, ISR0, IWR0 DMA Channel 3 (SPORT0 RX) IVG9 16 2 IAR2 IMASK0, ISR0, IWR0 DMA Channel 4 (SPORT0 TX) IVG9 17 2 IAR2 IMASK0, ISR0, IWR0 DMA Channel 5 (SPORT1 RX) IVG9 18 2 IAR2 IMASK0, ISR0, IWR0 DMA Channel 6 (SPORT1 TX) IVG9 19 2 IAR2 IMASK0, ISR0, IWR0 TWI IVG10 20 3 IAR2 IMASK0, ISR0, IWR0 DMA Channel 7 (SPI) IVG10 21 3 IAR2 IMASK0, ISR0, IWR0 DMA Channel 8 (UART0 RX) IVG10 22 3 IAR2 IMASK0, ISR0, IWR0 DMA Channel 9 (UART0 TX) IVG10 23 3 IAR2 IMASK0, ISR0, IWR0 DMA Channel 10 (UART1 RX) IVG10 24 3 IAR3 IMASK0, ISR0, IWR0 DMA Channel 11 (UART1 TX) IVG10 25 3 IAR3 IMASK0, ISR0, IWR0 Rev. D | Page 7 of 88 | July 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory NAND Flash Controller (NFC) One-Time Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports Serial Peripheral Interface (SPI) Port UART Ports TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode USB On-The-Go Dual-Role Device Controller Code Security with Lockbox Secure Technology Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage Regulation ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Lockbox Secure Technology Disclaimer Signal Descriptions Specifications Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Clock Related Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Clock Related Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing NAND Flash Controller Interface Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing HOSTDP A/C Timing- Host Read Cycle HOSTDP A/C Timing- Host Write Cycle 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 289-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide