Datasheet ADSP-BF522, ADSP-BF523, ADSP-BF524, ADSP-BF525, ADSP-BF526, ADSP-BF527 (Analog Devices) - 8

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ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 3. System Interrupt Controller (SIC) (Continued) General Purpose Default Peripheral Interrupt Event Interrupt (at RESET) Peripheral Interrupt ID Core Interrupt ID SIC Registers
OTP Memory Interrupt IVG11 26 4 IAR3 IMASK0, ISR0, IWR0 GP Counter IVG11 27 4 IAR3 IMASK0, ISR0, IWR0 DMA Channel 1 (MAC RX/HOSTDP) IVG11 28 4 IAR3 IMASK0, ISR0, IWR0 Port H Interrupt A IVG11 29 4 IAR3 IMASK0, ISR0, IWR0 DMA Channel 2 (MAC TX/NFC) IVG11 30 4 IAR3 IMASK0, ISR0, IWR0 Port H Interrupt B IVG11 31 4 IAR3 IMASK0, ISR0, IWR0 Timer 0 IVG12 32 5 IAR4 IMASK1, ISR1, IWR1 Timer 1 IVG12 33 5 IAR4 IMASK1, ISR1, IWR1 Timer 2 IVG12 34 5 IAR4 IMASK1, ISR1, IWR1 Timer 3 IVG12 35 5 IAR4 IMASK1, ISR1, IWR1 Timer 4 IVG12 36 5 IAR4 IMASK1, ISR1, IWR1 Timer 5 IVG12 37 5 IAR4 IMASK1, ISR1, IWR1 Timer 6 IVG12 38 5 IAR4 IMASK1, ISR1, IWR1 Timer 7 IVG12 39 5 IAR4 IMASK1, ISR1, IWR1 Port G Interrupt A IVG12 40 5 IAR5 IMASK1, ISR1, IWR1 Port G Interrupt B IVG12 41 5 IAR5 IMASK1, ISR1, IWR1 MDMA Stream 0 IVG13 42 6 IAR5 IMASK1, ISR1, IWR1 MDMA Stream 1 IVG13 43 6 IAR5 IMASK1, ISR1, IWR1 Software Watchdog Timer IVG13 44 6 IAR5 IMASK1, ISR1, IWR1 Port F Interrupt A IVG13 45 6 IAR5 IMASK1, ISR1, IWR1 Port F Interrupt B IVG13 46 6 IAR5 IMASK1, ISR1, IWR1 SPI Status IVG7 47 0 IAR5 IMASK1, ISR1, IWR1 NFC Status IVG7 48 0 IAR6 IMASK1, ISR1, IWR1 HOSTDP Status IVG7 49 0 IAR6 IMASK1, ISR1, IWR1 Host Read Done IVG7 50 0 IAR6 IMASK1, ISR1, IWR1 Reserved IVG10 51 3 IAR6 IMASK1, ISR1, IWR1 USB_INT0 Interrupt IVG10 52 3 IAR6 IMASK1, ISR1, IWR1 USB_INT1 Interrupt IVG10 53 3 IAR6 IMASK1, ISR1, IWR1 USB_INT2 Interrupt IVG10 54 3 IAR6 IMASK1, ISR1, IWR1 USB_DMAINT Interrupt IVG10 55 3 IAR6 IMASK1, ISR1, IWR1
Event Control
The processor provides a very flexible mechanism to control the written while in supervisor mode. (Note that general- processing of events. In the CEC, three registers are used to purpose interrupts can be globally enabled and disabled coordinate and control events. Each register is 16 bits wide. with the STI and CLI instructions, respectively.) • CEC interrupt latch register (ILAT) — Indicates when • CEC interrupt pending register (IPEND) — The IPEND events have been latched. The appropriate bit is set when register keeps track of all nested events. A set bit in the the processor has latched the event and cleared when the IPEND register indicates the event is currently active or event has been accepted into the system. This register is nested at some level. This register is updated automatically updated automatically by the controller, but it may be writ- by the controller but may be read while in supervisor mode. ten only when its corresponding IMASK bit is cleared. The SIC allows further control of event processing by providing • CEC interrupt mask register (IMASK) — Controls the three pairs of 32-bit interrupt control and status registers. Each masking and unmasking of individual events. When a bit is register contains a bit corresponding to each of the peripheral set in the IMASK register, that event is unmasked and is interrupt events shown in Table 3 on Page 7. processed by the CEC when asserted. A cleared bit in the • SIC interrupt mask registers (SIC_IMASKx) — Control the IMASK register masks the event, preventing the processor masking and unmasking of each peripheral interrupt event. from servicing the event even though the event may be When a bit is set in these registers, that peripheral event is latched in the ILAT register. This register may be read or Rev. D | Page 8 of 88 | July 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory NAND Flash Controller (NFC) One-Time Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports Serial Peripheral Interface (SPI) Port UART Ports TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode USB On-The-Go Dual-Role Device Controller Code Security with Lockbox Secure Technology Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage Regulation ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Lockbox Secure Technology Disclaimer Signal Descriptions Specifications Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Clock Related Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Clock Related Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing NAND Flash Controller Interface Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing HOSTDP A/C Timing- Host Read Cycle HOSTDP A/C Timing- Host Write Cycle 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 289-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide