Datasheet ADSP-BF542, ADSP-BF544, ADSP-BF547, ADSP-BF548, ADSP-BF549 (Analog Devices) - 6

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ADSP-BF542/ ADSP-BF544 /ADSP-BF547/ ADSP-BF548/ ADSP-BF549 MEMORY ARCHITECTURE
The ADSP-BF54x processors view memory as a single unified
FFFF 0x FFFF CORE MMR REGISTERS (2M BYTES)
4G byte address space, using 32-bit addresses. All resources,
0xFFE0 0000
including internal memory, external memory, and I/O control
SYSTEM MMR REGISTERS (2M BYTES) 0xFFC0 0000
registers, occupy separate sections of this common address
RESERVED 0xFFB0 1000
space. The memory portions of this address space are arranged
SCRATCHPAD SRAM (4K BYTES)
in a hierarchical structure to provide a good cost/performance
0xFFB0 0000 RESERVED
balance of some very fast, low-latency on-chip memory as cache
FF 0x A2 4000 L1 ROM (64K BYTE)
or SRAM, and larger, lower-cost and performance off-chip
FF 0x A1 4000
memory systems. See Figure 3 on Page 6.
INSTRUCTION SRAM / CACHE (16K BYTES) 0xFFA1 0000
The on-chip L1 memory system is the highest-performance
RESERVED 0xFFA0 C000
memory available to the Blackfin processor. The off-chip mem-
INSTRUCTION BANK B SRA M (16K BYTES) Y MAP 0xFFA0 8000
ory system, accessed through the external bus interface unit
INSTRUCTION BANK A SRA M (32K BYTES)
(EBIU), provides expansion with flash memory, SRAM, and
0xFFA0 0000 RESERVED
double-rate SDRAM (standard or mobile DDR), optionally
0xFF90 8000
accessing up to 768M bytes of physical memory.
DATA BANK B SRAM / CACHE (16K BYTES) 0xFF90 4000 DATA BANK B SRAM (16 K BYTES) INTERNAL MEMOR
Most of the ADSP-BF54x Blackfin processors also include an L2
FF90 0000 0x
SRAM memory array which provides up to 128K bytes of high
RESERVED 0xFF80 8000
speed SRAM, operating at one half the frequency of the core and
DATA BANK A SRAM / CACHE (16K BYTES) FF80 4000 0x
with slightly longer latency than the L1 memory banks (for
DATA BANK A SRAM (16 K BYTES)
information on L2 memory in each processor, see Table 1). The
0xFF80 0000 RESERVED
L2 memory is a unified instruction and data memory and can
FEB2 0x 0000
hold any mixture of code and data required by the system
L2 SRAM (128K BYTES) 0 FEB0 x 0000
design. The Blackfin cores share a dedicated low latency 64-bit
RESERVED EF00 0x 1000
data path port into the L2 SRAM memory.
B OOT ROM (4K BYTES) EF00 0x 0000
The memory DMA controllers (DMAC1 and DMAC0) provide
RESERVED 0x3000 0000
high-bandwidth data-movement capability. They can perform
ASYNC MEMORY BANK 3 (64M BYTES)
block transfers of code or data between the internal memory
0x2C00 0000 ASYNC MEMORY BANK 2 (64M BYTES) Y MAP
and the external memory spaces.
0x2800 0000 ASYNC MEMORY BANK 1 (64M BYTES) 0x2400 0000 Internal (On-Chip) Memory ASYNC MEMORY BANK 0 (64M BYTES) 0x2000 0000
The ADSP-BF54x processors have several blocks of on-chip
RESERVED TOP OF LAST
memory providing high bandwidth access to the core.
DDR PAGE DDR MEM BANK 1 (8M BYTES to 256M BYTES) EXTERNAL MEMOR
The first block is the L1 instruction memory, consisting of
DDR MEM BANK 0 (8M BYTES to 256M BYTES)
64K bytes of SRAM, of which 16K bytes can be configured as a
0x0000 0000
four-way set-associative cache or as SRAM. This memory is accessed at full processor speed. Figure 3. ADSP-BF547/ADSP-BF548/ADSP-BF549 The second on-chip memory block is the L1 data memory, con- Internal/External Memory Map1 sisting of 64K bytes of SRAM, of which 32K bytes can be 1 For ADSP-BF544 processors, L2 SRAM is 64K Bytes configured as a two-way set-associative cache or as SRAM. This (0xFEB0000–0xFEB0FFFF). For ADSP-BF542 processors, there is no L2 memory block is accessed at full processor speed. SRAM. The third memory block is a 4K byte scratchpad SRAM, which
External (Off-Chip) Memory
runs at the same speed as the L1 memories. It is only accessible as data SRAM and cannot be configured as cache memory. Through the external bus interface unit (EBIU), the The fourth memory block is the factory programmed L1 ADSP-BF54x Blackfin processors provide glueless connectivity instruction ROM, operating at full processor speed. This ROM to external 16-bit wide memories, such as DDR and mobile is not customer-configurable. DDR SDRAM, SRAM, NOR flash, NAND flash, and FIFO devices. To provide the best performance, the bus system of the The fifth memory block is the L2 SRAM, providing up to 128K DDR and mobile DDR interface is completely separate from the bytes of unified instruction and data memory, operating at one other parallel interfaces. Furthermore, the DDR controller sup- half the frequency of the core. ports either standard DDR memory or mobile DDR memory. Finally, there is a 4K byte boot ROM connected as L3 memory. See the Ordering Guide on Page 101 for details. Throughout It operates at full SCLK rate. this document, references to “DDR” are intended to cover both the standard and mobile DDR standards. Rev. E | Page 6 of 102 | March 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time-Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Interface Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Controller Area Network (CAN) TWI Controller Interface Ports General-Purpose I/O (GPIO) Pin Interrupts Pixel Compositor (PIXC) Enhanced Parallel Peripheral Interface (EPPI) USB On-the-Go Dual-Role Device Controller ATA/ATAPI-6 Interface Keypad Interface Secure Digital (SD)/SDIO Controller Code Security Media Transceiver MAC Layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Domains Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) MXVR Board Layout Guidelines Additional information Related Signal Chains Lockbox Secure Technology Disclaimer Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing DDR SDRAM/Mobile DDR SDRAM Clock and Control Cycle Timing DDR SDRAM/Mobile DDR SDRAM Timing DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing External Port Bus Request and Grant Cycle Timing NAND Flash Controller Interface Timing Synchronous Burst AC Timing External DMA Request Timing Enhanced Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing SD/SDIO Controller Timing MXVR Timing HOSTDP A/C Timing-Host Read Cycle HOSTDP A/C Timing-Host Write Cycle ATA/ATAPI-6 Interface Timing USB On-The-Go-Dual-Role Device Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Typical Rise and Fall Times Thermal Characteristics 400-Ball CSP_BGA Package Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide