Datasheet ADSP-BF542, ADSP-BF544, ADSP-BF547, ADSP-BF548, ADSP-BF549 (Analog Devices) - 7

link to page 101 link to page 101 link to page 18
ADSP-BF542 /ADSP-BF544 /ADSP-BF547/ ADSP-BF548 /ADSP-BF549
The DDR memory controller can gluelessly manage up to two • Support for SLC (single level cell) NAND flash devices banks of double-rate synchronous dynamic memory (DDR and unlimited in size, with page sizes of 256 bytes and 512 mobile DDR SDRAM). The 16-bit interface operates at the bytes. Larger page sizes can be supported in software. SCLK frequency, enabling a maximum throughput of 532M • The ability to release external bus interface pins during bytes/s. The DDR and mobile DDR controller is augmented long accesses. with a queuing mechanism that performs efficient bursts into the DDR and mobile DDR. The controller is an industry stan- • Support for internal bus requests of 16 bits or 32 bits. dard DDR and mobile DDR SDRAM controller with each bank • A DMA engine to transfer data between internal memory supporting from 64M bit to 512M bit device sizes and 4-, 8-, or and a NAND flash device. 16-bit widths. The controller supports up to 256M bytes per external bank. With 2 external banks, the controller supports up
One-Time-Programmable Memory
to 512M bytes total. Each bank is independently programmable The ADSP-BF54x Blackfin processors have 64K bits of one- and is contiguous with adjacent banks regardless of the sizes of time-programmable (OTP) non-volatile memory that can be the different banks or their placement. programmed by the developer only one time. It includes the Traditional 16-bit asynchronous memories, such as SRAM, array and logic to support read access and programming. Addi- EPROM, and flash devices, can be connected to one of the four tionally, its pages can be write protected. 64M byte asynchronous memory banks, represented by four OTP enables developers to store both public and private data memory select strobes. Alternatively, these strobes can function on-chip. In addition to storing public and private key data for as bank-specific read or write strobes preventing further glue applications requiring security, it also allows developers to store logic when connecting to asynchronous FIFO devices. See the completely user-definable data such as a customer ID, product Ordering Guide on Page 101 for a list of specific products that ID, or a MAC address. By using this feature, generic parts can be provide support for DDR memory. shipped, which are then programmed and protected by the In addition, the external bus can connect to advanced flash developer within this non-volatile memory. The OTP memory device technologies, such as: can be accessed through an API provided by the on-chip ROM. • Page-mode NOR flash devices
I/O Memory Space
• Synchronous burst-mode NOR flash devices The ADSP-BF54x Blackfin processors do not define a separate • NAND flash devices I/O space. All resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers Customers should consult the Ordering Guide when selecting a mapped into memory-mapped registers (MMRs) at addresses specific ADSP-BF54x component for the intended application. near the top of the 4G byte address space. These are separated Products that provide support for mobile DDR memory are into two smaller blocks, one containing the control MMRs for noted in the ordering guide footnotes. all core functions and the other containing the registers needed
NAND Flash Controller (NFC)
for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and The ADSP-BF54x Blackfin processors provide a NAND Flash appear as reserved space to on-chip peripherals. Controller (NFC) as part of the external bus interface. NAND flash devices provide high-density, low-cost memory. However,
Booting
NAND flash devices also have long random access times, invalid The ADSP-BF54x Blackfin processors contain a small on-chip blocks, and lower reliability over device lifetimes. Because of boot kernel, which configures the appropriate peripheral for this, NAND flash is often used for read-only code storage. In booting. If the ADSP-BF54x Blackfin processors are configured this case, all DSP code can be stored in NAND flash and then to boot from boot ROM memory space, the processor starts exe- transferred to a faster memory (such as DDR or SRAM) before cuting from the on-chip boot ROM. For more information, see execution. Another common use of NAND flash is for storage Booting Modes on Page 18. of multimedia files or other large data segments. In this case, a software file system may be used to manage reading and writing
Event Handling
of the NAND flash device. The file system selects memory seg- ments for storage with the goal of avoiding bad blocks and The event controller on the ADSP-BF54x Blackfin processors equally distributing memory accesses across all address loca- handles all asynchronous and synchronous events to the proces- tions. Hardware features of the NFC include: sors. The ADSP-BF54x Blackfin processors provide event handling that supports both nesting and prioritization. Nesting • Support for page program, page read, and block erase of allows multiple event service routines to be active simultane- NAND flash devices, with accesses aligned to page ously. Prioritization ensures that servicing of a higher-priority boundaries. event takes precedence over servicing of a lower-priority event. • Error checking and correction (ECC) hardware that facili- tates error detection and correction. • A single 8-bit or 16-bit external bus interface for com- mands, addresses, and data. Rev. E | Page 7 of 102 | March 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time-Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Interface Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Controller Area Network (CAN) TWI Controller Interface Ports General-Purpose I/O (GPIO) Pin Interrupts Pixel Compositor (PIXC) Enhanced Parallel Peripheral Interface (EPPI) USB On-the-Go Dual-Role Device Controller ATA/ATAPI-6 Interface Keypad Interface Secure Digital (SD)/SDIO Controller Code Security Media Transceiver MAC Layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Domains Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) MXVR Board Layout Guidelines Additional information Related Signal Chains Lockbox Secure Technology Disclaimer Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing DDR SDRAM/Mobile DDR SDRAM Clock and Control Cycle Timing DDR SDRAM/Mobile DDR SDRAM Timing DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing External Port Bus Request and Grant Cycle Timing NAND Flash Controller Interface Timing Synchronous Burst AC Timing External DMA Request Timing Enhanced Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing SD/SDIO Controller Timing MXVR Timing HOSTDP A/C Timing-Host Read Cycle HOSTDP A/C Timing-Host Write Cycle ATA/ATAPI-6 Interface Timing USB On-The-Go-Dual-Role Device Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Typical Rise and Fall Times Thermal Characteristics 400-Ball CSP_BGA Package Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide