Datasheet ADSP-BF539, ADSP-BF539F (Analog Devices) - 6

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ADSP-BF539/ ADSP-BF539F
The PC133-compliant SDRAM controller can be programmed The flash chip enable pin FCE must be connected to AMS0 or to interface to up to 128M bytes of SDRAM. The SDRAM con- AMS3–1 through a printed circuit board trace. When connected troller allows one row to be open for each internal SDRAM to AMS0, the Blackfin processor can boot from the flash die. bank, for up to four internal SDRAM banks, improving overall When connected to AMS3–1, the flash memory appears as non- system performance. volatile memory in the processor memory map, shown in The asynchronous memory controller can be programmed to Figure 3. control up to four banks of devices with very flexible timing
Flash Memory Programming
parameters for a wide variety of devices. Each bank occupies a 1M byte segment regardless of the size of the devices used, so The ADSP-BF539F8 flash memory can be programmed before that these banks will only be contiguous if each is fully popu- or after mounting on the printed circuit board. lated with 1M byte of memory. To program the flash prior to mounting on the printed circuit board, use a hardware programming tool that can provide the
Flash Memory (ADSP-BF539F Only)
data, address, and control stimuli to the flash die through the The ADSP-BF539F8 processor contains a separate flash die, external pins on the package. During this programming, VDDEXT connected to the EBIU bus, within the package of the processor. and GND must be provided to the package and the Blackfin Figure 4 shows how the flash memory die and Blackfin proces- must be held in reset with bus request (BR) asserted and a sor die are connected. CLKIN provided. The ADSP-BF539F8 contains an 8M bit (512K × 16-bit) bottom The VisualDSP++ tools can be used to program the flash mem- boot sector Spansion S29AL008J known good die flash memory. ory after the device is mounted on a printed circuit board. Additional information for this product can be found in the
Flash Memory Sector Protection
Spansion data sheet at www.spansion.com. Features include the following: To use the sector protection feature, a high voltage (+8.5 V to +12.5 V) must be applied to the flash FRESET pin. Refer to the • Access times as fast as 70 ns (EBIU registers must be set flash data sheet for details. appropriately) • Sector protection
I/O Memory Space
• One million write cycles per sector Blackfin processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On- • 20 year data retention chip I/O devices have their control registers mapped into mem-
0
ory mapped registers (MMRs) at addresses near the top of the
- -
4G byte address space. These are separated into two smaller
Y A15 T A
blocks, one of which contains the control MMRs for all core
ADDR19 ARE AWE ARD D GND VDDEXT
functions, and the other of which contains the registers needed for setup and control of the on-chip peripherals outside of the
ADDR19-1 A18-0
core. The MMRs are accessible only in supervisor mode and
ARE OE AWE WE
appear as reserved space to on-chip peripherals.
ARDY RY/BY DATA15-0 DQ15-0 Booting GND VSS V VCC DDEXT
The ADSP-BF539/ADSP-BF539F processors contain a small
BYTE S29AL008J FLASH DIE AMS3-0 CE
boot kernel, which configures the appropriate peripheral for
RESET RESET
booting. If the processors are configured to boot from boot B
WP
ROM memory space, they start executing from the on-chip boot ROM. For more information, see Booting Modes on Page 16.
ADSP-BF539F PACKAGE Event Handling 0 - NC
The event controller handles all asynchronous and synchronous
FCE RESET
events to the processor. The processors provide event handling
AMS3 FRESET
that supports both nesting and prioritization. Nesting allows Figure 4. Internal Connection of Flash Memory (ADSP-BF539F8) multiple event service routines to be active simultaneously. Pri- oritization ensures that servicing of a higher priority event takes The Blackfin processor connects to the flash memory die with precedence over servicing of a lower priority event. The control- address, data, chip enable, write enable, and output enable con- ler provides support for five different types of events: trols as if it were an external memory device. Note that the write-protect input pin to the flash is not connected and inac- • Emulation – An emulation event causes the processor to cessible, disabling this feature. enter emulation mode, allowing command and control of the processor via the JTAG interface. • Reset – This event resets the processor. Rev. F | Page 6 of 60 | October 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF539/ADSP-BF539F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF539F Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports Programmable I/O Pins Programmable Flags (GPIO Port F) General-Purpose I/O Ports C, D, and E Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Media Transceiver MAC layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Example Connections and Layout Considerations MXVR Board Layout Guidelines Voltage Regulator Layout Guidelines Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing MXVR Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide