Datasheet ADSP-BF539, ADSP-BF539F (Analog Devices) - 5

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ADSP-BF539/ ADSP-BF539F
The address arithmetic unit provides two addresses for simulta- neous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit index, modify,
0xFFFF FFFF
length, and base registers (for circular buffering), and eight
CORE MMR REGISTERS (2M BYTES)
additional 32-bit pointer registers (for C-style indexed stack
0xFFE0 0000 SYSTEM MMR REGISTERS (2M BYTES)
manipulation).
0xFFC0 0000 RESERVED
Blackfin processors support a modified Harvard architecture in
0xFFB0 1000 SCRATCHPAD SRAM (4K BYTES)
combination with a hierarchical memory structure. Level 1 (L1)
0xFFB0 0000 P
memories are those that typically operate at the full processor
RESERVED A 0xFFA1 4000 M
speed with little or no latency. At the L1 level, the instruction
INSTRUCTION SRAM / CACHE (16K BYTES) Y R 0xFFA1 0000
memory holds instructions only. The two data memories hold
O INSTRUCTION SRAM (64K BYTES) M E
data, and a dedicated scratchpad data memory stores stack and
0xFFA0 0000 M RESERVED L
local variable information.
A 0xFF90 8000 DATA BANK B SRAM / CACHE (16K BYTES) RN
In addition, multiple L1 memory blocks are provided, offering a
E 0xFF90 4000 T DATA BANK B SRAM (16K BYTES)
configurable mix of SRAM and cache. The memory manage-
IN 0xFF90 0000
ment Unit (MMU) provides memory protection for individual
RESERVED 0xFF80 8000
tasks that can be operating on the core and can protect system
DATA BANK A SRAM / CACHE (16K BYTES)
registers from unintended access.
0xFF80 4000 DATA BANK A SRAM (16K BYTES)
The architecture provides three modes of operation: user mode,
0xFF80 0000 RESERVED
supervisor mode, and emulation mode. User mode has
0xEF00 0000 RESERVED
restricted access to certain system resources, thus providing a
P 0x2040 0000 A
protected software environment, while supervisor mode has
ASYNC MEMORY BANK 3 (1M BYTES) OR M ON-CHIP FLASH (ADSP-BF539F ONLY) Y
unrestricted access to the system and core resources.
0x2030 0000 OR ASYNC MEMORY BANK 2 (1M BYTES) OR M
The Blackfin processor instruction set has been optimized so
E ON-CHIP FLASH (ADSP-BF539F ONLY) M 0x2020 0000
that 16-bit opcodes represent the most frequently used instruc-
L ASYNC MEMORY BANK 1 (1M BYTES) OR A N
tions, resulting in excellent compiled code density. Complex
ON-CHIP FLASH (ADSP-BF539F ONLY) R 0x2010 0000 E
DSP instructions are encoded into 32-bit opcodes, representing
ASYNC MEMORY BANK 0 (1M BYTES) OR XT E ON-CHIP FLASH (ADSP-BF539F ONLY)
fully featured multifunction instructions. Blackfin processors
0x2000 0000
support a limited multi-issue capability, where a 32-bit instruc-
RESERVED 0x0800 0000
tion can be issued in parallel with two 16-bit instructions,
SDRAM MEMORY (16M BYTES TO 128M BYTES)
allowing the programmer to use many of the core resources in a
0x0000 0000
single instruction cycle. The Blackfin processor assembly language uses an algebraic syn- Figure 3. ADSP-BF539/ADSP-BF539F Internal/External Memory Map tax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C++ compiler,
Internal (On-Chip) Memory
resulting in fast and efficient software implementations. The ADSP-BF539/ADSP-BF539F processor has three blocks of
MEMORY ARCHITECTURE
on-chip memory, providing high bandwidth access to the core. The first is the L1 instruction memory, consisting of 80K bytes The ADSP-BF539/ADSP-BF539F processors view memory as a SRAM, of which 16K bytes can be configured as a four-way set- single unified 4G byte address space, using 32-bit addresses. All associative cache. This memory is accessed at full processor resources, including internal memory, external memory, and speed. I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are The second on-chip memory block is the L1 data memory, con- arranged in a hierarchical structure to provide a good cost/per- sisting of two banks of up to 32K bytes each. Each memory bank formance balance of some very fast, low latency on-chip is configurable, offering both cache and SRAM functionality. memory as cache or SRAM, and larger, lower cost and perfor- This memory block is accessed at full processor speed. mance off-chip memory systems. See Figure 3. The third memory block is a 4K byte scratch pad SRAM, which The L1 memory system is the primary highest performance runs at the same speed as the L1 memories, but is only accessible memory available to the Blackfin processor. The off-chip mem- as data SRAM and cannot be configured as cache memory. ory system, accessed through the external bus interface unit
External (Off-Chip) Memory
(EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 132M bytes of physical External memory is accessed via the EBIU. This 16-bit interface memory. provides a glueless connection to a bank of synchronous DRAM The memory DMA controller provides high bandwidth data (SDRAM) as well as up to four banks of asynchronous memory movement capability. It performs block transfers of code or data devices including flash, EPROM, ROM, SRAM, and memory between the internal memory and the external memory spaces. mapped I/O devices. Rev. F | Page 5 of 60 | October 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF539/ADSP-BF539F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF539F Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports Programmable I/O Pins Programmable Flags (GPIO Port F) General-Purpose I/O Ports C, D, and E Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Media Transceiver MAC layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Example Connections and Layout Considerations MXVR Board Layout Guidelines Voltage Regulator Layout Guidelines Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing MXVR Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide