Datasheet ADSP-BF538, ADSP-BF538F (Analog Devices) - 6

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ADSP-BF538/ ADSP-BF538F External (Off-Chip) Memory
The Blackfin processor connects to the flash memory die with address, data, chip enable, write enable, and output enable con- External memory is accessed via the external bus interface unit trols as if it were an external memory device. Note that the (EBIU). This 16-bit interface provides a glueless connection to a write-protect input pin to the flash is not connected and inac- bank of synchronous DRAM (SDRAM) as well as up to four cessible, disabling this feature. banks of asynchronous memory devices including flash, EPROM, ROM, SRAM, and memory mapped I/O devices. The flash chip enable pin FCE must be connected to AMS0 or AMS3–1 through a printed circuit board trace. When connected The PC133-compliant SDRAM controller can be programmed to AMS0, the Blackfin processor can boot from the flash die. to interface to up to 128M bytes of SDRAM. The SDRAM con- When connected to AMS3–1, the flash memory appears as non- troller allows one row to be open for each internal SDRAM volatile memory in the processor memory map, shown in bank, for up to four internal SDRAM banks, improving overall Figure 3. system performance. The asynchronous memory controller can be programmed to
Flash Memory Programming
control up to four banks of devices with very flexible timing The ADSP-BF538F8 flash memory can be programmed before parameters for a wide variety of devices. Each bank occupies a or after mounting on the printed circuit board. 1M byte segment regardless of the size of the devices used, so To program the flash prior to mounting on the printed circuit that these banks will only be contiguous if each is fully popu- board, use a hardware programming tool that can provide the lated with 1M byte of memory. data, address, and control stimuli to the flash die through the
Flash Memory (ADSP-BF538F8 Only)
external pins on the package. During this programming, VDDEXT and GND must be provided to the package and the Blackfin The ADSP-BF538F8 processor contains a separate flash die, must be held in reset with bus request (BR) asserted and a connected to the EBIU bus, within the package of the processor. CLKIN provided. Figure 4 shows how the flash memory die and Blackfin proces- sor die are connected. The VisualDSP++ tools can be used to program the flash mem- ory after the device is mounted on a printed circuit board. The ADSP-BF538F8 contains an 8M bit (512K × 16-bit) bottom boot sector Spansion S29AL008J known good die flash memory.
Flash Memory Sector Protection
For additional information, visit www.spansion.com. Features To use the sector protection feature, a high voltage (+12 V nom- include the following: inal) must be applied to the flash FRESET pin. Refer to the flash • Access times as fast as 70 ns (EBIU registers must be set data sheet for details. appropriately)
I/O Memory Space
• Sector protection Blackfin processors do not define a separate I/O space. All • One million write cycles per sector resources are mapped through the flat 32-bit address space. On- • 20 year data retention chip I/O devices have their control registers mapped into mem- ory mapped registers (MMRs) at addresses near the top of the
1 0
4G byte address space. These are separated into two smaller
- -
blocks, one which contains the control MMRs for all core func-
Y A15 T A
tions, and the other which contains the registers needed for
ADDR19 ARE AWE ARD D GND VDDEXT
setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear
ADDR19-1 A18-0
as reserved space to on-chip peripherals.
ARE OE AWE WE ARDY RY/BY Booting DATA15-0 DQ15-0 GND VSS
The ADSP-BF538/ADSP-BF538F processors contain a small
V VCC DDEXT
boot kernel, which configures the appropriate peripheral for
BYTE S29AL008J FLASH DIE AMS3-0 CE
booting. If the processor is configured to boot from boot ROM
RESET RESET
memory space, the processor starts executing from the on-chip B
WP
boot ROM. For more information, see Booting Modes on Page 16.
ADSP-BF538F PACKAGE Event Handling 0 - FCE NC
The event controller on the ADSP-BF538/ADSP-BF538F pro-
RESET
cessors handle all asynchronous and synchronous events to the
AMS3 FRESET
processors. The processor provides event handling that sup- Figure 4. Internal Connection of Flash Memory (ADSP-BF538F8) ports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization Rev. E | Page 6 of 60 | November 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF538/ADSP-BF538F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF538F8 Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports General-Purpose Ports Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide