Datasheet ADSP-BF538, ADSP-BF538F (Analog Devices)

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Blackfin Embedded Processor ADSP-BF538/ ADSP-BF538F FEATURES PERIPHERALS Up to 533 MHz high performance Blackfin processor Parallel peripheral interface (PPI) supporting ITU-R 656 video Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, data formats 40-bit shifter 4 dual-channel, full-duplex synchronous serial ports, RISC-like register and instruction model for ease of supporting 16 stereo I2S channels programming and compiler friendly support 2 DMA controllers supporting 26 peripheral DMAs Advanced debug, trace, and performance monitoring 4 memory-to-memory DMAs Wide range of operating voltages (see Operating Conditions Controller area network (CAN) 2.0B controller on Page 23) 3 SPI-compatible ports Programmable on-chip voltage regulator Three 32-bit timer/counters with PWM support 316-ball Pb-free CSP_BGA package 3 UARTs with support for IrDA MEMORY 2 TWI controllers compatible with I2C industry standard Up to 54 general-purpose I/O pins (GPIO) Up to 148K bytes of on-chip memory (see Table 1 on Page 3 ) Real-time clock, watchdog timer, and 32-bit core timer Optional 8M bit parallel flash with boot option On-chip PLL capable of frequency multiplication Memory management unit providing memory protection Debug/JTAG interface External memory controller with glueless support for SDRAM, SRAM, flash, and ROM Flexible memory booting options from SPI and external memory VOLTAGE REGULATOR JTAG TEST AND EMULATION PERIPHERAL ACCESS BUS S U B TWI0-1 CAN 2.0B
B
INTERRUPT WATCHDOG CONTROLLER CCESS A TIMER GPIO PORT RTC C GPIO L1 L1 PERIPHERAL DMA DMA PPI INSTRUCTION DATA SPI1-2 CONTROLLER1 CONTROLLER0 GPIO MEMORY MEMORY GPIO PORT 0 TIMER0-2 S PORT 1 D U S B F UART 1-2 U B DMA CORE DMA DMA DMA SPI0 BUS 1 EXTERNAL CORE EXTERNAL GPIO CCESS SPORT2-3 BUS 1 BUS 0 BUS 0 A CCESS PORT A UART0 E EXTERNAL PORT DMA DMA FLASH, SDRAM CONTROL SPORT0-1 16 8M BIT P ARALLEL FLASH BOOT ROM (SEE TABLE 1)
Figure 1. Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
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Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF538/ADSP-BF538F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF538F8 Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports General-Purpose Ports Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide