Datasheet ADSP-BF561 (Analog Devices) - 7

link to page 7 ADSP-BF561 writing the appropriate values into the Interrupt Assignment
Table 2. System Interrupt Controller (SIC) (Continued)
Registers (SIC_IAR7–0). Table 2 describes the inputs into the
Default
SIC and the default mappings into the CEC.
Peripheral Interrupt Event Mapping Table 2. System Interrupt Controller (SIC)
Timer7 Interrupt IVG10 Timer8 Interrupt IVG10
Default Peripheral Interrupt Event Mapping
Timer9 Interrupt IVG10 PLL Wakeup IVG7 Timer10 Interrupt IVG10 DMA1 Error (Generic) IVG7 Timer11 Interrupt IVG10 DMA2 Error (Generic) IVG7 Programmable Flags 15–0 Interrupt A IVG11 IMDMA Error IVG7 Programmable Flags 15–0 Interrupt B IVG11 PPI0 Error IVG7 Programmable Flags 31–16 Interrupt A IVG11 PPI1 Error IVG7 Programmable Flags 31–16 Interrupt B IVG11 SPORT0 Error IVG7 Programmable Flags 47–32 Interrupt A IVG11 SPORT1 Error IVG7 Programmable Flags 47–32 Interrupt B IVG11 SPI Error IVG7 DMA1 Channel 12/13 Interrupt IVG8 (Memory DMA/Stream 0) UART Error IVG7 DMA1 Channel 14/15 Interrupt IVG8 Reserved IVG7 (Memory DMA/Stream 1) DMA1 Channel 0 Interrupt (PPI0) IVG8 DMA2 Channel 12/13 Interrupt IVG9 DMA1 Channel 1 Interrupt (PPI1) IVG8 (Memory DMA/Stream 0) DMA1 Channel 2 Interrupt IVG8 DMA2 Channel 14/15 Interrupt IVG9 DMA1 Channel 3 Interrupt IVG8 (Memory DMA/Stream 1) DMA1 Channel 4 Interrupt IVG8 IMDMA Stream 0 Interrupt IVG12 DMA1 Channel 5 Interrupt IVG8 IMDMA Stream 1 Interrupt IVG12 DMA1 Channel 6 Interrupt IVG8 Watchdog Timer Interrupt IVG13 DMA1 Channel 7 Interrupt IVG8 Reserved IVG7 DMA1 Channel 8 Interrupt IVG8 Reserved IVG7 DMA1 Channel 9 Interrupt IVG8 Supplemental Interrupt 0 IVG7 DMA1 Channel 10 Interrupt IVG8 Supplemental Interrupt 1 IVG7 DMA1 Channel 11 Interrupt IVG8 DMA2 Channel 0 Interrupt (SPORT0 Rx) IVG9
Event Control
DMA2 Channel 1 Interrupt (SPORT0 Tx) IVG9 The ADSP-BF561 provides the user with a very flexible mecha­ DMA2 Channel 2 Interrupt (SPORT1 Rx) IVG9 nism to control the processing of events. In the CEC, three DMA2 Channel 3 Interrupt (SPORT1 Tx) IVG9 registers are used to coordinate and control events. Each of the registers is 16 bits wide, while each bit represents a particular DMA2 Channel 4 Interrupt (SPI) IVG9 event class. DMA2 Channel 5 Interrupt (UART Rx) IVG9 • CEC Interrupt Latch Register (ILAT) – The ILAT register DMA2 Channel 6 Interrupt (UART Tx) IVG9 indicates when events have been latched. The appropriate DMA2 Channel 7 Interrupt IVG9 bit is set when the processor has latched the event and DMA2 Channel 8 Interrupt IVG9 cleared when the event has been accepted into the system. DMA2 Channel 9 Interrupt IVG9 This register is updated automatically by the controller, but may also be written to clear (cancel) latched events. This DMA2 Channel 10 Interrupt IVG9 register may be read while in supervisor mode and may DMA2 Channel 11 Interrupt IVG9 only be written while in supervisor mode when the corre­ Timer0 Interrupt IVG10 sponding IMASK bit is cleared. Timer1 Interrupt IVG10 • CEC Interrupt Mask Register (IMASK) – The IMASK reg­ Timer2 Interrupt IVG10 ister controls the masking and unmasking of individual Timer3 Interrupt IVG10 events. When a bit is set in the IMASK register, that event is Timer4 Interrupt IVG10 unmasked and will be processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, Timer5 Interrupt IVG10 thereby preventing the processor from servicing the event Timer6 Interrupt IVG10 Rev. E | Page 7 of 64 | September 2009 Document Outline Features Peripherals Table of Contents Revision History General Description Portable Low Power Architecture Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port Programmable Flags (PFx) Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode-Maximum Performance Active Operating Mode-Moderate Power Savings Sleep Operating Mode-High Dynamic Power Savings Deep Sleep Operating Mode-Maximum Dynamic Power Savings Hibernate State-Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools EZ-KIT Lite Evaluation Board Designing an Emulator-Compatible Processor Board Related Documents Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port- Master Timing Serial Peripheral Interface (SPI) Port- Slave Timing Universal Asynchronous Receiver Transmitter (UART) Port-Receive and Transmit Timing Programmable Flags Cycle Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Power Dissipation Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 256-Ball CSP_BGA (17 mm) Ball Assignment 256-Ball CSP_BGA (12 mm) Ball Assignment 297-Ball PBGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide